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Scroll Title

anchor	Table_SIP_JTG
title	JTAG pins connection

Scroll Table Layout

JTAG Signal	Connected to	Note
TMS	Lattice MachXO, U15 BankArtix 7 FPGA, U1	Bank 2 Bank 0
TDI	Lattice MachXO, U15 Artix 7 FPGA, U1	Bank 2 Bank 0
TDO	Lattice MachXO, U15 Artix 7 FPGA, U1	Bank 2 Bank 0
TCK	Lattice MachXO, U15 Artix 7 FPGA, U1	Bank 2 Bank 0
INIT	Artix 7 FPGA, U1	Connected to 1.8

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Scroll Title

anchor	Table_OBP
title	On board peripherals

Scroll Table Layout

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Scroll Title

anchor	Table_OBP_SPI
title	Quad SPI interface MIOs and pins

Scroll Table Layout

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Scroll Title

anchor	Table_OBP_PCLK
title	Programmable Clock Generator Inputs and Outputs

Scroll Table Layout

Si5345A Pin	Signal Name / Description	Connected To	Direction	Note
IN0	Reference input clock.	U11	Input	25.00 MHz oscillator, SiT8008BI
IN1	FMCT_GBTCLK0	J6E	Input	FMC Pcam Adapter
IN2	FMCT_GBTCLK1	J6E	Input	FMC Pcam Adapter
IN3	FMCT_CLK0	J6E	Input	FMC Pcam Adapter
XAXB	-	GND	Input	54.0000 MHz XTAL CX3225SB
SCLK	PLL_SCL	J8, U20	Input	EEPROM Programming
SDA	PLL_SDA	J8, U20	Input	EEPROM Programming
OUT0	GA_PCLK	U5/U1	Output	FPGA bank 15
OUT1	GB_PCLK	U6/U1	Output	FPGA bank 15
OUT2	GC_PCLK	U7/U1	Output	FPGA bank 15
OUT3	GD_PCLK	U8/U1	Output	FPGA bank 15
OUT4	CLK4_P	U1H	Output
OUT5	GBTCLK0	J1E/J6E	Output
OUT6	GBTCLK1	J1E/J6E	Output
OUT7	GBTCLK0	J1E	Output
OUT8/OUT9	CLK8	Not Conneted	Output	Not Used	OUT9	/CLK9	Not Conneted	Output	Not Used

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