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Scroll Title
anchorTable_SIP_JTG
titleJTAG pins connection

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JTAG Signal

Connected to

Note
TMS

Lattice MachXO, U15

BankArtix 7 FPGA, U1

Bank 2

Bank 0

TDI

Lattice MachXO, U15

Artix 7 FPGA, U1

Bank 2

Bank 0

TDO

Lattice MachXO, U15

Artix 7 FPGA, U1

Bank 2

Bank 0

TCK

Lattice MachXO, U15

Artix 7 FPGA, U1

Bank 2

Bank 0

INIT

Artix 7 FPGA, U1

Connected to 1.8

MIO Pins

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hiddentrue
idComments

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:


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SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

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On-board Peripherals

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idComments

Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

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anchorFigure_PWR_PD
titlePower Distribution


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Scroll Title
anchorFigure_PWR_PS
titlePower Sequency


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