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Table of Contents

Table of Contents

Overview

The Trenz Electronic TEF0003 is a FPGA Mezzanine Card (FMC) integrated with an Artix 7 FPGA, 512 Mb Flash Memory.

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Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Key Features

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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features' must be split into 6 main groups:

FPGA/Module
- Package:
- Speed:
- Temperature:
RAM/Storage
- E.g. SDRAM, SPI
On Board
- E.g. CPLD, PLL
Interface
- E.g. ETH, USB, B2B, Display port
Power
- E.g. Input supply voltage
Dimension

FPGA: Xilinx Artix 7 (XC7A100T)
- Package: FGG484 (Compatible with
- Speed: -1 (Slowest)
- Temperature: Industrial Grade (–40°C to +100°C)
RAM/Storage:
- 1x NOR SPI FLASH (128M x 4)
- 1x EEPROM (16K x 8)
On Board:
- 4x Deserializer IC (3.12 Gbps)
- 4x I²C and SMBus I/O Expander
- 1x Programable Clock Generator
- 1x Clock Generator
Interface:
- 2x VITA 57 SEAM/SEAF Series
- 4x Coaxial Connectors
Power:
- 4x Voltage Regulators
- 3.3 Supply Voltage
Dimension: 72 mm x 65 mm

Block Diagram

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add drawIO object here.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

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title	TEF0003 block diagram

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Main Components

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Notes :

Picture of the PCB (top and bottom side) with labels of important components
Add List below

Note
For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .

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Coaxial Connectors, J2-5
SPI Flash, U9
Xilinx Artix 7 FPGA, U1
Lattice MachXO FPGA, U15
FMC Adapter, J1
EEPROM, U4
I2C Switches, U2, U17-20
Jumper, J7
Serializer, U5-8
Connector Header, J8
Oscillator 25MHz, U11
Programmable Clock Generator, U10
FMC Adapter, J6

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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title	Initial delivery state of programmable devices on the module

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Storage device name	Content	Notes
SPI Flash	Not programmed
EEPROM	Not Programmed
Clock Generator	Programmed

Configuration Signals

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Overview of Boot Mode, Reset, Enables.

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title	Reset Process.

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Signal	Description	Note
PRSNT_TOP	Lattice MachXO Configuration Pin
PROG_B	Artix 7 Configuration Pin	Connected to 1.8

Signals, Interfaces and Pins

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Notes :

For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- SD
- USB
- ETH
- FMC
- ...
For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
- JTAG
- UART
- I2C
- MGT
- ...

FMC Connectors

FPGA bank number and number of I/O signals connected to the FMC Connectors J1 and J6 which are located on top and bottom of the board.

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title	General PL I/O to FMC Connectors information

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FPGA	FPGA Bank	Connector Designator	I/O Signal Count	Voltage Level	Notes
Artix 7, U1	16	J1B	68 Single Ended, 34 Differential	1.8V
Artix 7, U1	35	J6B	68 Single Ended, 34 Differential	1.8V
Lattice MachXO, U	0	J1F	4 Single Ended	3.3V	CPLD
Lattice MachXO, U	0	J6F	4 Single Ended	3.3V	CPLD

JTAG Interface

The Lattice MachXO (U15) is available to meet the requirement of a CPLD, JTAG access to the MachXO is available through FMC Adapter J6. JTAG access to the Artix 7(U1) is available via MachXO, Bank 2.

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title	JTAG pins connection

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JTAG Signal	Connected to	Note
TMS	Lattice MachXO, U15 BankArtix 7 FPGA, U1	Bank 2 Bank 0
TDI	Lattice MachXO, U15 Artix 7 FPGA, U1	Bank 2 Bank 0
TDO	Lattice MachXO, U15 Artix 7 FPGA, U1	Bank 2 Bank 0
TCK	Lattice MachXO, U15 Artix 7 FPGA, U1	Bank 2 Bank 0
INIT	Artix 7 FPGA, U1	Connected to 1.8

On-board Peripherals

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Notes :

add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs

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Chip/Interface	Designator	Notes
SPI Flash	U9
EEPROM	U4
Oscillators	U11,U10

Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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title	Quad SPI interface MIOs and pins

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Schematic	U9 Pin	Notes
SPI-CS	CS
SPI-CLK	CLK
SPI-DQO	DI/IO0
SPI_DQ3	HOLD/IO3
SPI-DQ2	WP/IO2
SPI-DQ1	DO/IO1
1.8V	VCC

EEPROM

A microchip serial EEPROM (U4) is provided for IPMI data. It is accessible via the LPC FMC connector J1 (SCL, SDA).

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I2C Address	Designator	Notes
0x50	U4

Clock Sources

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title	Osillators

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Designator	Description	Frequency	Note
U4	Oscillator	25 MHz
U10	Programmable Clock Generator	Variable

Programmable Clock Generator

There is a Silicon Labs I²C programmable clock generator on-board (U10) to generate reference clocks for the module. Programming can be done using I²C via PIN header J8. The I²C Address is 0x69.

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anchor	Table_OBP_PCLK
title	Programmable Clock Generator Inputs and Outputs

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Si5345A Pin	Signal Name / Description	Connected To	Direction	Note
IN0	Reference input clock.	U11	Input	25.00 MHz oscillator, SiT8008BI
IN1	FMCT_GBTCLK0	J6E	Input	FMC Pcam Adapter
IN2	FMCT_GBTCLK1	J6E	Input	FMC Pcam Adapter
IN3	FMCT_CLK0	J6E	Input	FMC Pcam Adapter
XAXB	-	GND	Input	54.0000 MHz XTAL CX3225SB
SCLK	PLL_SCL	J8, U20	Input	EEPROM Programming
SDA	PLL_SDA	J8, U20	Input	EEPROM Programming
OUT0	GA_PCLK	U5/U1	Output	FPGA bank 15
OUT1	GB_PCLK	U6/U1	Output	FPGA bank 15
OUT2	GC_PCLK	U7/U1	Output	FPGA bank 15
OUT3	GD_PCLK	U8/U1	Output	FPGA bank 15
OUT4	CLK4_P	U1H	Output
OUT5	GBTCLK0	J1E/J6E	Output
OUT6	GBTCLK1	J1E/J6E	Output
OUT7	GBTCLK0	J1E	Output
OUT8/OUT9	CLK8/CLK9	Pulled low	Output

Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

Power on-sequence
Power distribution
Voltage monitoring circuit

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

Power Supply

Power supply with minimum current capability of 3 A for system startup is recommended.

Power Consumption

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title	Power Consumption

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Power Input Pin	Typical Current
VIN	TBD*

* TBD - To Be Determined

Power Distribution Dependencies

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anchor	Figure_PWR_PD
title	Power Distribution

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Power-On Sequence

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title	Power Sequency

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Power Rails

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title	Module power rails.

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Power Rail Name	FMC Adapter J1G Pin	FMC Adapter J6G Pin	Direction
12V	C35, C37	C35, C37	Input
3P3VAUX	D32	D32	Input
3P3V	D36, D38, D40, C39	D36, D38, D40, C39	Input
VREFA	H1	H1	Input
VREFB	K1	K1	Input
VIOB	J39, K40	J39, K40	Input
VADJ	H40, G39, F40, E39	H40, G39, F40, E39	Input

Bank Voltages

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anchor	Table_PWR_BV
title	Zynq SoC bank voltages.

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Bank	Schematic Name	Voltage	Notes
Bank 13	VCCO_13	1.8 V
Bank 14	VCCO_14	1.8 V
Bank 15	VCCO_15	1.8 V
Bank 16	VCCO_16	VADJ	1.8 V
Bank 34	VCCO_34	1.8 V
Bank 35	VCCO_35	VADJ	1.8 V
Bank 0	VCCO_0	1.8 V

Technical Specifications

Absolute Maximum Ratings

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anchor	Table_TS_AMR
title	PS absolute maximum ratings

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Symbols	Description	Min	Max	Unit
12V	Input Supply Voltage	-12	12	V
T_STG	Storage Temperature	-40	85	°C

Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

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anchor	Table_TS_ROC
title	Recommended operating conditions.

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Parameter	Min	Max	Units	Reference Document
12V	12	12	V
T_OPR	-40	85	°C	See MT25QU512ABB8E12-0SIT (U9) datasheet.

Physical Dimensions

Module size: 84 mm × 65 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: 10 mm.

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title	Physical Dimension

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Scroll Only

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scroll-html	true

Currently Offered Variants

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Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

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anchor	Table_VCP_SO
title	Trenz Electronic Shop Overview

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Trenz shop TEF0003 overview page
English page	German page

Revision History

Hardware Revision History

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Set correct links to download arrier, e.g. TE0706 REV02:

TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

Date format: YYYY-MM-DD

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anchor	Figure_RV_HRN
title	Board hardware revision number.

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Document Change History

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Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports

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Date

Revision

Contributor

Description

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prefix	v.
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Page info

infoType	Modified by
type	Flat
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Initial Release

--

all

Page info

infoType	Modified users
type	Flat
showVersions	false

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Disclaimer

Include Page

	IN:Legal Notices
	IN:Legal Notices

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Trenz Electronic Documentation

Versions Compared

Old Version 36

New Version 37

Key

Overview

Key Features

Block Diagram

Main Components

Initial Delivery State

Configuration Signals

Signals, Interfaces and Pins

FMC Connectors

JTAG Interface

On-board Peripherals

Quad SPI Flash Memory

EEPROM

Clock Sources

Programmable Clock Generator

Power and Power-On Sequence

Power Supply

Power Consumption

Power Distribution Dependencies

Power-On Sequence

Power Rails

Bank Voltages

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Document Change History

Disclaimer