...
| Scroll Title |
|---|
| anchor | Table_SIP_CPLDJTG |
|---|
| title | CPLD JTAG pins connection |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
JTAG Signal | B2B Connector |
|---|
| FMC_TMS | J6F-TCK | | FMC_TDI_TOP | J6F-J1-TDI | | FMC_TDO_TOP | J6F-TDO | | FMC_TCK | J6F-TCK | | JTAGENJ7 | Pulled down |
|
| Scroll Title |
|---|
| anchor | Table_SIP_JTG |
|---|
| title | JTAG pins connection |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
JTAG Signal | Connected to | Note |
|---|
| TMS | Lattice MachXO, U15 BankArtix 7 FPGA, U1 | Bank 2 Bank 0 | | TDI | Lattice MachXO, U15 Artix 7 FPGA, U1 | Bank 2 Bank 0 | | TDO | Lattice MachXO, U15 Artix 7 FPGA, U1 | Bank 2 Bank 0 | | TCK | Lattice MachXO, U15 Artix 7 FPGA, U1 | Bank 2 Bank 0 | | INIT | Artix 7 FPGA, U1 | Connected to 1.8 |
|
...
There is a Silicon Labs I2C programmable clock generator on-board (U10) in order to generate reference clocks for the module. Programming can be done using I2C via PIN header J8. The I2C Address is 0x69.
| Scroll Title |
|---|
| anchor | Table_OBP_PCLK |
|---|
| title | Programmable Clock Generator Inputs and Outputs |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
Si5345A Pin
| Signal Name / Description
| Connected To | Direction | Note |
|---|
IN0 | Reference input clock. | U11 | Input | 25.00 MHz oscillator, SiT8008BI | | IN1 | FMCT_GBTCLK0 | J6E | Input | FMC Pcam Adapter | | IN2 | FMCT_GBTCLK1 | J6E | Input | FMC Pcam Adapter | | IN3 | FMCT_CLK0 | J6E | Input | FMC Pcam Adapter | XAXB | - | GND | Input | 54.0000 00 MHz XTAL CX3225SB | | SCLK | PLL_SCL | J8, U20 | Input | EEPROM Programming | | SDA | PLL_SDA | J8, U20 | Input | EEPROM Programming | | OUT0 | GA_PCLK | U5/U1 | Output | FPGA bank 15 | | OUT1 | GB_PCLK | U6/U1 | Output | FPGA bank 15 | | OUT2 | GC_PCLK | U7/U1 | Output | FPGA bank 15 | | OUT3 | GD_PCLK | U8/U1 | Output | FPGA bank 15 | | OUT4 | CLK4_P | U1H | Output |
| | OUT5 | GBTCLK0 | J1E/J6E | Output |
| | OUT6 | GBTCLK1 | J1E/J6E | Output |
| | OUT7 | GBTCLK0 | J1E | Output |
| | OUT8/OUT9 | CLK8/CLK9 | Pulled low | Output |
|
|
...