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Scroll Title |
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anchor | Table_SIP_SFP+ |
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title | SFP+ Connector Information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Pin | Connected to | Notes |
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VCCR | 3.3V |
| VCCT | 3.3V |
| VREF | GND |
| TD+/TD- | MGT TX | MGT Lane | RD+/RD- | MGT RX | MGT Lane | TX/FAULT | SFP0_TX_FAUL | SFP_CTRL | TX/DISABLE | SFP0_TX_DIS | SFP_CTRL | MOD-DEF2 | SFP0_SDA | SFP_CTRL | MOD-DEF1 | SFP0_SCL | SFP_CTRL | MOD-DEF0 | SFP0_MT_DEF0 | SFP_CTRL | RS0/RS1 | SFP0_RS0_1 | SFP_CTRL | LOS | SFP0_LOS | SFP_CTRL |
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There are two SMT Pin Headers, J26-J27.
J26 is available to choose voltage level for VCCIO34 (FPGA Bank 34) and J27 is provided to set the voltage level for of V_CFG (Configuration Voltage). In order to set the voltage level, you should connect it to the corresponding pin with the target value voltage.
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Scroll Title |
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anchor | Table_PWR_PC |
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title | Power Consumption |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Input Pin | Typical Current |
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VIN3 | .3V* TBD |
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* TBD - To Be Determined
Power Distribution Dependencies
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Scroll Title |
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anchor | Table_PWR_PR |
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title | Module power rails. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Power Rail Name | B2B Connector JM1 Pin | B2B Connector JM2 Pin | Direction | Notes |
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3.3V | 99,97 | - | Input |
| 1.8V | - | 18 | Input |
| 3.3V_OUT | 83 | 54 | Output | Comes from Module |
| VCCIO34 | 61 | - | OutputInput | Variable voltage level | V_CFG0 | 53 | - | Input | Variable voltage level |
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Board to Board Connectors
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