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Overview

The Trenz Electronic TE0xxx-xx ... TE0022-01 board is an industrial-grade ... module ... based on Xilinx ...SoC module based on Intel Cyclone V FPGA, a Ethernet PHY, one GByte DDR3 SDRAM per HPS and FPGA, two 32 MByte Quad SPI Flash memory for configuration and operation and powerful switching-mode power supplies for all on-board voltages.

Refer to http://trenz.org/tec0850tei0022-info for the current online version of this manual and other available documentation.

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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features' must be split into 6 main groups for modues:

SoC/FPGA
- Package:
- Speed:
- Temperature:
RAM/Storage
- E.g. SDRAM, SPI
On Board
- E.g. CPLD, PLL
Interface
- E.g. ETH, USB, B2B, Display port
Power
- E.g. Input supply voltage
Dimension

Key Features' must be split into 6 main groups for carrier:

Modules
- TE0808, TE807, TE0803,...
RAM/Storage
- E.g. SDRAM, SPI
On Board
- E.g. CPLD, PLL
Interface
- E.g. ETH, USB, B2B, Display port
Power
- E.g. Input supply voltage
Dimension

Modules/ SoC FPGA
- Intel Cyclone V (5CSEMA5F31C8N)
- Package: FBGA 896 pins
- Speed: 8
- Temperature: Commercial (Tj = 0 °C to 85 °C)TE0808, TE807, TE0803,...
RAM/Storage
- E.g. SDRAM, SPI
- 1 GByte DDR3 SDRAM for HPS
- 1 GByte DDR3 SDRAM for FPGA
- 32 MByte SPI for HPS
- 32 MByte SPI for FPGA
On Board
On Board
- Ethernet
- JTAG
- UART
- SD Card
- FMC
- Intel MAX10
- HDMI
- PMOD
- USB
- E.g. CPLD, PLL
Interface
- E.g. ETH, USB, B2B, Display port
Power
- E.g. Input supply voltage
Dimension

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Scroll Title

anchor	Table_OBP_ETH
title	Ethernet PHY to Zynq SoC connectionsto Zynq SoC connections

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Bank	Signal Name	ETH1	ETH2	Signal Description

CAN Transceiver

Scroll Title

anchor	Table_OBP_CAN
title	CAN Tranciever interface MIOs

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Bank

Signal Name

ETH1

ETH2

Signal Description

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	Schematic	U?? Pin	Notes
	D-Tx		Driver Input
	R-Rx		Reciever Output

Clock Sources

Scroll Title

anchor	Table_OBP_CANCLK
title	CAN Tranciever interface MIOsOsillators

Scroll Table Layout

style	widths
orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Bank

Schematic

U?? Pin

Notes

D-Tx

Driver Input

R-Rx

Reciever Output

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repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Designator	Description	Frequency	Note
U2	Ethernet	25 MHz
U37	FPGA	50 MHz	Bank 5B and MAX10
U35	FPGA	50 MHz	Bank 4A and 3B

U44	HPS	24 MHz	CLK1, CLK2
U32	FTDI	12 MHz
U3	HDMI	12 MHz
U34	USB	24 MHz


	HPS	25 MHz	CLK1 HPS SOCKIT
	HPS	25 MHz	CLK2 HPS SOCKIT
	FPGA	50 MHz	Bank 3B SOCKIT
	FPGA	50 MHz	Bank 4A SOCKIT
	FPGA	50 MHz	Bank 5B SOCKIT
	FPGA	50 MHz	Bank 8A SOCKIT
	FPGA	50 MHz	Pin P8/9 SOCKIT

Scroll Title

anchor	Table_OBP_CLK
title	Osillators

Scroll Table Layout

orientation

portrait

sortDirection

ASC

repeatTableHeaders

default

style

widths

sortByColumn

1

sortEnabled

false

cellHighlighting

true

KHz

Designator	Description	Frequency	Note
MHz	MHz

Trenz Electronic Documentation

Versions Compared

Old Version 1

New Version 2

Key

Overview

CAN Transceiver

Clock Sources

Power and Power-On Sequence