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  • SoC FPGA
    • Intel Cyclone V (5CSEMA5F31C8N)
    • Package: FBGA 896 pins
    • Speed: 8
    • Temperature: Commercial (Tj = 0 °C to 85 °C)
  • RAM/Storage
    • 1 GByte DDR3 SDRAM for HPS
    • 1 GByte DDR3 SDRAM for FPGA
    • 32 MByte SPI for HPS
    • 32 MByte SPI for FPGA
  • On Board
    • 4 x SMA Connector
    • Temperature Sensor
    • Intel MAX10E.g. CPLD, PLL
  • Interface
    • LPC FMC Connector
    • 4 x PMOD Connector
    • JTAG via micro USB B Connector
    • UART via
    • micro USB B Connector
    • 4 x USB 2.0
    • Ethernet via RJ45 Connector
    • SD Card
    • HDMI
  • Power
    • 12 V Input supply voltage
  • Dimension
    • 360 160 mm x 160 130 mm


Block Diagram

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add drawIO object here.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
anchorTable_SIP_B2B
titleGeneral PL I/O to B2B connectors information

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FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
































JTAG Interface

JTAG access to the TExxxx SoM through B2B connector JMXAccording to the JTAGEN and JTAGSEL[1..0] pins the management Intel MAX10, the Intel Cyclone V HPS, the Intel Cyclone V FPGA or the FMC can be accessed.

JTAG_EN
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anchorTable_SIP_JTG
titleJTAG pins connection

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JTAGSEL1

JTAGSEL0

JTAGSEL1

JTAGSEL0
XXONIntel MAX10
ONONOFFIntel Cyclone V HPS
ONOFFOFFIntel Cyclone V FPGA
OFFONOFFFMC

JTAG Signal

B2B Connector

TMSTDITDOTCK


MIO Pins

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI


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