...
- SoC FPGA
- Intel Cyclone V (5CSEMA5F31C8N)
- Package: FBGA 896 pins
- Speed: 8
- Temperature: Commercial (Tj = 0 °C to 85 °C)
- RAM/Storage
- 1 GByte DDR3 SDRAM for HPS
- 1 GByte DDR3 SDRAM for FPGA
- 32 MByte SPI for HPS
- 32 MByte SPI for FPGA
- On Board
- 4 x SMA Connector
- Temperature Sensor
- Intel MAX10E.g. CPLD, PLL
- Interface
- LPC FMC Connector
- 4 x PMOD Connector
- JTAG via micro USB B Connector
- UART via
- micro USB B Connector
- 4 x USB 2.0
- Ethernet via RJ45 Connector
- SD Card
- HDMI
- Power
- 12 V Input supply voltage
- Dimension
Block Diagram
Page properties |
---|
|
add drawIO object here.
|
...
Scroll Title |
---|
anchor | Table_SIP_B2B |
---|
title | General PL I/O to B2B connectors information |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
---|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
JTAG Interface
JTAG access to the TExxxx SoM through B2B connector JMXAccording to the JTAGEN and JTAGSEL[1..0] pins the management Intel MAX10, the Intel Cyclone V HPS, the Intel Cyclone V FPGA or the FMC can be accessed.
Scroll Title |
---|
anchor | Table_SIP_JTG |
---|
title | JTAG pins connection |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
JTAGSEL1 | JTAGSEL0 | JTAGSEL1 | JTAGSEL0 |
---|
X | X | ON | Intel MAX10 | ON | ON | OFF | Intel Cyclone V HPS | ON | OFF | OFF | Intel Cyclone V FPGA | OFF | ON | OFF | FMC |
JTAG Signal | B2B Connector |
---|
TMS | TDI | TDO | TCK | JTAG_EN
|
MIO Pins
Page properties |
---|
|
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin | Connected to | B2B | Notes |
---|
MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
|
...