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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
LPC FMC Connector
The FMC (FPGA Mezzanine Card) connector J4 with low pin count (LPC) provides as an ANSI/VITA 57.1 standard a modular interface to the Intel Cyclone V FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.
The connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.
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| anchor | Table_SIP_B2BFMC |
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| title | General PL I/O to B2B FMC connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FMC Signal | Intel Cyclone V Direction | FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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| LA0...1 | RX and TX | 4 SE, 2 Diff | FMC_VADJ | Connected to RX and TX pins at the Intel Cyclone V | | LA2...15 | RX | 28 SE, 14 Diff | FMC_VADJ |
| | LA16 | TX | 2 SE, 1 Diff | FMC_VADJ |
| | LA17...18 | RX | 4 SE, 2 Diff | FMC_VADJ |
| | LA19...33 | TX | 28 SE, 14 Diff | FMC_VADJ |
| | CLK0...1 | RX | 4 SE, 2 Diff | FMC_VADJ |
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JTAG Interface
According to the JTAGEN and JTAGSEL[1..0] pins the management Intel MAX10, the Intel Cyclone V HPS, the Intel Cyclone V FPGA or the FMC can be accessed.
| Scroll Title |
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAGSEL1 | JTAGSEL0 | JTAGSEL1 | JTAGSEL0 |
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| X | X | ON | Intel MAX10 | | ON | ON | OFF | Intel Cyclone V HPS | | ON | OFF | OFF | Intel Cyclone V FPGA | | OFF | ON | OFF | FMC |
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MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: | MIO Pin | Connected to | B2B | Notes |
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| MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI |
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According to the JTAGEN and JTAGSEL[1..0] pins the management Intel MAX10, the Intel Cyclone V HPS, the Intel Cyclone V FPGA or the FMC can be accessed.
| Scroll Title |
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| anchor | Table_SIPOBP_JTGMIOs |
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| title | JTAG MIOs pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAGSEL1| JTAGSEL0 | JTAGSEL1 | JTAGSEL0 | | X | X | ON | Intel MAX10 | | ON | ON | OFF | Intel Cyclone V HPS | | ON | OFF | OFF | Intel Cyclone V FPGA | | OFF | ON | OFF | FMC | |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: |
| MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3 SPI_SCK | J2 | QSPI
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| anchor | Table_OBP_MIOs |
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| title | MIOs pinsOn board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Connected to | B2B | Notes |
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| Chip/Interface | Designator | Notes |
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Quad SPI Flash Memory
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes :
In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsectionMinimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
| Scroll Title |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U?? Pin | Notes |
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RTC
| Scroll Title |
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| anchor | Table_OBP_RTC |
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| title | On board peripheralsI2C interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Chip/Interface | Designator | Notes |
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Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
| MIO Pin | Schematic | U? Pin | Notes |
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| Scroll Title |
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| anchor | Table_OBP_SPII2C_RTC |
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| title | Quad SPI interface MIOs and pinsI2C Address for RTC |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | U?? Pin| I2C Address | Designator | Notes |
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EEPROM
| Scroll Title |
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| anchor | Table_OBP_RTCEEP |
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| title | I2C EEPROM interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U?? Pin | Notes |
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| Scroll Title |
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| anchor | Table_OBP_I2C_RTCEEPROM |
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| title | I2C Address address for RTCEEPROM |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | I2C Address | Designator | Notes |
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LEDs
| Scroll Title |
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| anchor | Table_OBP_EEPLED |
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| title | I2C EEPROM interface MIOs and pinsOn-board LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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MIO Pin| Designator | Schematic | U?? Pin | Notes |
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| Scroll Title |
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| anchor | Table_OBP_I2C_EEPROM |
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| title | I2C address for EEPROM |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | I2C Address | Designator | Notes |
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LEDs
| Color | Connected to | Active Level | Note |
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| D11 | Green | Intel Cyclone V HPS | L | User LED | | D12 | Green | Intel Cyclone V HPS | L | User LED | | D13 | Green | Intel Cyclone V FPGA | L | User LED | | D14 | Green | Intel Cyclone V FPGA | L | User LED | | D8 | Green | Intel Cyclone V FPGA | L | Status: Configuration "Done" | | D15 | Green | FT234XD | L | UART | | D18 | Green | UART TX | H | UART | | D19 | Green | UART RX | H | UART |
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| Scroll Title |
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| anchor | Table_OBP_LED |
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| title | On-board LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Color | Connected to | Active Level | Note |
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DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE???? TEI0022 SoM has ??? one GByte volatile DDR3 SDRAM IC memory per FPGA and HPS for storing user application code and data.
- Part number: IS43TR16512BL-125KBLI
- Supply voltage: 1.35 V
- Speed: NOR Flash???
- Temperature: TC = -40 °C up to 95 °C
Ethernet
| Scroll Title |
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| anchor | Table_OBP_ETH |
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| title | Ethernet PHY to Zynq SoC HPS connections |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Bank | Signal Name | ETH1 | ETH2 | Signal Description |
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CAN Transceiver
| false |
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| cellHighlighting | true |
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| Bank | Signal Name | ETH | Signal Description |
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| 7B | ETH_TXCK |
| RGMII Transmit Reference Clock | | 7B | ETH_TXD0 |
| RGMII Transmit Data 0 | | 7B | ETH_TXD1 |
| RGMII Transmit Data 1 | | 7B | ETH_TXD2 |
| RGMII Transmit Data 2 | | 7B | ETH_TXD3 |
| RGMII Transmit Data 3 | | 7B | ETH_TXCTL |
| RGMII Transmit Control | | 7B | ETH_RXCK |
| RGMII Receive Reference Clock | | 7B | ETH_RXD0 |
| RGMII Receive Data 0 | | 7B | ETH_RXD1 |
| RGMII Receive Data 2 | | 7B | ETH_RXD2 |
| RGMII Receive Data 3 | | 7B | ETH_RXD3 |
| RGMII Receive Data 4 | | 7B | ETH_RXCTL |
| RGMII Receive Control | | 7C | ETH_RST |
| Reset | | 7B | ETH_MDC |
| Management Data Clock | | 7B | ETH_MDIO |
| Management Data I/O | | 7B | PHY_INT |
| Interrupt |
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| Scroll Title |
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| anchor | Table_OBP_CAN |
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| title | CAN Tranciever interface MIOs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Bank | Schematic | U?? Pin | Notes |
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D-Tx | Driver Input | R-Rx | Reciever Output
Clock Sources
| Scroll Title |
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| anchor | Table_OBP_CLK |
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| title | Osillators |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Description | Frequency | Note |
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| U2 | Ethernet | 25 MHz |
| | U37 | FPGA | 50 MHz | Bank 5B and MAX10 | | U35 | FPGA | 50 MHz | Bank 4A and 3B |
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| | U44 | HPS | 24 MHz | CLK1, CLK2 | | U32 | FTDI | 12 MHz |
| | U3 | HDMI | 12 MHz |
| | U34 | USB | 24 MHz |
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| HPS | 25 MHz | CLK1 HPS SOCKIT |
| HPS | 25 MHz | CLK2 HPS SOCKIT |
| FPGA | 50 MHz | Bank 3B SOCKIT |
| FPGA | 50 MHz | Bank 4A SOCKIT |
| FPGA | 50 MHz | Bank 5B SOCKIT |
| FPGA | 50 MHz | Bank 8A SOCKIT |
| FPGA | 50 MHz | Pin P8/9 SOCKIT |
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