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The Trenz Electronic TEBT0808 is a test fixture for module TE0808(REV01REV02, REV02REV03) and TE0803(REV01) series.

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Note:
Use 'Key Features' description in shoping page, for example: https://shop.trenz-electronic.de/de/TE0728-04-1Q-SoC-Micromodul-mit-Xilinx-Automotive-Zynq-7020-512-MByte-DDR3L-6-x-6-cm

  • Modules
    • TE0808, TE0803,...
  • On Board
    • Done/Error/Status LEDs
    • MEMS Oscillator 125.0 00 MHz
    • Boot Mode DIP-Switch
    • 2x DIP-Switches to control TE080x power domains
  • Interface
    • Pin Header for TE0790 JTAG/UART Adapter
    • ARM JTAG header
    • 10 Pin Header for I2C
    • Board to Board (B2B) Connectors
    • One PL GT with 4x SMA Connectors
    • One PS GT with 4x SMA Connectors
    • One pre-assembled TE0790 XMOD FTDI JTAG adapter
  • Power:
    • 3.3 V (Nominal supply voltageSupply Voltage)
  • Dimension:
    • 90mm x 90mm

Block Diagram

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titleTEBT0808 Block Diagram


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Main Components

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titleTEBT0808 Main Components


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  1. Uninsulated Power Jack. J7-J8
  2. SMA Coaxial straight. J6- J9...15
  3. Surface Mount Schottky Barrier Rectifier. D1
  4. ARM PJTAG Pin Header J16
  5. I2C Pin Header, J5
  6. Board to Board Connectors. J1...4
  7. MEMS Oscillator, U2
  8. On-Board LEDs, D2...4
  9. DIP-Switch, S1...3
  10. XMOD JTAG Base, JX1

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Board to Board (B2B) I/Os

TEBT0808 has four B2B Connectors and each connector has 160 pins. FPGA bank number and number of I/O signals connected to the B2B connector:

Scroll Title
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titleGeneral PL I/O to B2B connectors information

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B2B ConnectorInterfacesNumber of I/ONotes
J1

User I/O

22 46 Single Ended, 11 23 Differential

8 16 Single Ended, 4 8 Differential8

16 Single Ended, 4 8 Differential8

16 Single Ended, 4 8 Differential

3 4 Single Ended

Connected to Module FPGA, Bank 66

Connected to Module FPGA, Bank 228

Connected to Module FPGA, Bank 229

Connected to Module FPGA, Bank 230

VCCO_66, PL_1V8

J2

User IO

32 28 Single Ended, 16 14 Differential

4 6 Single Ended, 16 3 Differential

Connected to  Module FPGA, Bank 505

Connected to Module FPGA, Bank 128

Boot Mode 4 Single EndedMODE0...3
Control Signals15 Single EndedPLL_SEL0, PLL_SEL1, PLL_RST, EN_GTR, EN_PL, PLL_LOLN, EN_PSGT, ERR_STATUS, ERR_OUT,SRST_B, INIT_B, PROG_B, EN_FPD , EN_LPD , DONE
Power Control Signal10 Single EndedEN_PLL_PWR, PLL_FINC ,PG_PLL_1V8, LP_GOOD, PG_DDR, PG_PL, PG_FPD, PG_PSGT, PG_GT_R, PG_GT_L
JTAG Interface7 Single EndedTCK, TDI, TMS, TDO, MR, Rxd, Txd
WANNE2I2C 2 Single EndedPLL_SCL, PLL_SDA
Clock

6 Single Ended, 3 Differential

CLK0, CLK7, CLK8

J3



User I/OIO

12 Single Ended, 6 Differential

12 Single Ended, 6 Differential

Connected to Module FPGA, Bank 48

Connected to Module FPGA, Bank 47

Clock6 Single Ended, 3 DifferentialCLK228, CLK229, CLK230
PJTAG Interface7 Single EndedPJTAG0_TCK, PJTAG0_TDI, PJTAG0_TMS, PJTAG0_TDO,
MIO27 Single EndedMIO19..76
UART2 Single EndedTXD, RXD
Power pins4 Single EndedPS_1V8, SI_PLL_1V8, VCCO_48, VCCO_47
J4User I/O

48 Single Ended, 62 Differential

4 Single Ended

Connected to Module FPGA, Bank 64

Connected to Module FPGA, Bank 64

Power pins4 Single EndedVCCO_64, VCCO65


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