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The Trenz Electronic TE0022-01 board is an industrial-grade SoC module based on Intel Cyclone V FPGA, a Ethernet an ethernet PHY, one GByte DDR3 SDRAM per HPS and FPGA, two one 32 MByte Quad SPI Flash memory for configuration and operation per HPS and FPGA, and powerful switching-mode power supplies for all on-board voltages.
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Chip/Interface | Designator | Notes |
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| Temperature Sensor | U16 | DDR3 SDRAM | U26...29 |
| | QSPI | Ethernet | U1 | SPI | U6, U15 |
| | EEPROM | U38 |
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| | Intel Cyclone V | U10 |
| | SD Card | J3 |
| | Switch | S2 |
| | JTAG | U21 |
| | UART | U30 |
| | HDMI | U23 |
| | Intel MAX10 | U41 |
| | PMOD | P1...4 |
| | Power Monitoring | U54 |
| | USB | U8 |
| | Ethernet | U1 |
| | DDR3 SDRAM | U26...29 |
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Temperatur Sensor
The temperature sensor ADT7410 is implemented on the TEI0022 board.
Quad SPI Flash Memory
| Page properties |
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
| Scroll Title |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U?? Pin | Notes |
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| anchor | Table_OBP_RTC |
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| title | I2C interface MIOs and pins |
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There are two QSPI flash memory components implemented. One of them is used for the HPS (U6) and the other for the FPGA (U15). The flash memory is connected to its specific interface.
EEPROM
On the board are two EEPROMs used. One is used for the JTAG configuration (U31). The other is used for the ethernet MAC (U38). The last one is connected via I2C connection as specified in the table.
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EEPROM
| Scroll Title |
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| anchor | Table_OBP_EEP |
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| title | I2C EEPROM interface MIOs and pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U?? Pin | Notes |
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| Scroll Title |
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| anchor | Table_OBP_I2C_EEPROM |
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| title | I2C address for EEPROM |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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MIO | Pin | I2C Address | Designator | Notes |
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| HPS: A25, H23 | 0x50 | U38 | Ethernet MAC |
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LEDs
| Scroll Title |
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| anchor | Table_OBP_LED |
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| title | On-board LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Color | Connected to | Active Level | Note |
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| D11 | Green | Intel Cyclone V HPS | L | User LED | | D12 | Green | Intel Cyclone V HPS | L | User LED | | D13 | Green | Intel Cyclone V FPGA | L | User LED | | D14 | Green | Intel Cyclone V FPGA | L | User LED | | D8 | Green | Intel Cyclone V FPGA | L | Status: Configuration "Done" | | D15 | Green | FT234XD | L | UART | | D18 | Green | UART TX | H | UART | | D19 | Green | UART RX | H | UART | | D21 | Green | +12.0V | H | Status of +12.0V voltage rail | | D1 | Green | +12.0V_FMC | H | Status of +12.0V_FMC voltage rail | | D2 | Green | +5.0V | H | Status of +5.0V voltage rail | | D3 | Green | +3.3V | H | Status of +3.3V voltage rail | | D20 | Green | +3.3V_MAX10 | H | Status of +3.3V_MAX10 voltage rail | | D22 | Green | +3.3V_FMC | H | Status of +3.3V_FMC voltage rail | | D4 | Green | +2.5V | H | Status of +2.5V voltage rail | | D5 | Green | +1.8V | H | Status of +1.8V voltage rail | | D7 | Green | VCC | H | Status of VCC voltage rail | | D9 | Green | FMC_VADJ | H | Status of FMC_VADJ voltage rail | | D6 | Green | VDD_DDR_FPGA | H | Status of VDD_DDR_FPGA voltage rail | | D23 | Green | VDD_DDR_HPS | H | Status of VDD_DDR_HPS voltage rail | | D17 | Green | VTT_DDR_FPGA | H | Status of VTT_DDR_FPGA voltage rail | | D10 | Green | VTT_DDR_HPS | H | Status of VTT_DDR_HPS voltage rail |
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| Scroll Title |
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| anchor | Table_OBP_CLK |
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| title | Osillators |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Description | Frequency | Note |
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| U2 | Ethernet | 25 MHz |
| | U37 | FPGA | 50 MHz | Bank 5B and MAX10 | | U35 | FPGA | 50 MHz | Bank 4A and 3B |
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| | U44 | HPS | 24 25 MHz | CLK1, CLK2 | | U32 | FTDI | 12 MHz |
| | U3 | HDMI | 12 MHz |
| | U34 | USB | 24 MHz |
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| HPS | 25 MHz | CLK1 HPS SOCKIT |
| HPS | 25 MHz | CLK2 HPS SOCKIT |
| FPGA | 50 MHz | Bank 3B SOCKIT |
| FPGA | 50 MHz | Bank 4A SOCKIT |
| FPGA | 50 MHz | Bank 5B SOCKIT |
| FPGA | 50 MHz | Bank 8A SOCKIT |
| FPGA | 50 MHz | Pin P8/9 SOCKIT |
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