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Temperature Sensor U16 QSPI U6, U15 EEPROM U38 LED D1...15, D17...23 DDR3 SDRAM U26...29 Ethernet U1 Clock Sources U... Switch S2 JTAG U21 UART U30 HDMI U23 Intel MAX10 U41 PMOD P1...4 Power Monitoring U54 USB U8 SD Card J3 Intel Cyclone V U10

Temperatur Sensor

The temperature sensor ADT7410 is implemented on the TEI0022 board.

Quad SPI Flash Memory

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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

There are two QSPI flash memory components implemented. One of them is used for the HPS (U6) and the other for the FPGA (U15). The flash memory is connected to its specific interface.

I2C

The TEI0022 provides two independent I2C busses. One bus is used to connect the FMC I2C with the Intel Cyclone V HPS. The other bus is used to handle the on-board I2C devices.

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anchor Table_OBP_I2C title On-board peripherals' I2C-interfaces device slave addresses
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Bus I2C Device Designator I2C Address Schematic Names of I2C Bus Lines Notes HPS I2C Temperature Sensor 0x4A U16 HPS_I2C_SCL / HPS_I2C_SDA 3.3 V reference voltage HPS I2C EEPROM 0x50 U38 HPS_I2C_SCL / HPS_I2C_SDA 3.3 V reference voltage HPS I2C HDMI 0x72 U23 HPS_I2C_SCL / HPS_I2C_SDA 3.3 V reference voltage HPS FMC I2C FMC 0x50 J4 FMC_SCL / FMC_SDA 3.3 V reference voltage

System Controller Intel MAX10

The TEI0022 is equipped with an Intel MAX10 (U41) which is the central system management unit where essential control signals are logically linked by the implemented logic of the FPGA firmware. This generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and buttons between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller. Other tasks of the System Controller are the monitoring of the power-on sequence and configuration of the Intel Cyclone V FPGA. The functionalities and configuration of the pins depend on its firmware.

EEPROM

The TEI0022 board contains two EEPROMs for configuration and general user purposes.

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anchor Table_OBP_EEPROM title On-board configuration EEPROMs overview
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true EEPROM Model I2C Address Designator Memory Density Purpose Notes 24AA025E48T-I/OT 0x50 U38 2 KBit Ethernet MAC 93AA56BT-I/OT - U31 2 KBit JTAG Configuration

High-speed USB ULPI PHY

USB PHY (U8) is provided by USB3320C from Microchip. The ULPI interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V and PHY reference clock input is supplied from the on-board 24.0 MHz oscillator (U34).

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anchor Table_OBP_USB_PHY title USB PHY interface connections
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true PHY Pin Connected to Notes ULPI Intel Cyclone V HPS (U10) REFCLK 24 MHz from on board oscillator (U34) REFSEL[0..2] High (3.3 V) RESETB Intel Cyclone V HPS (U10) DP, DM 4-port USB 2.0 Hub (U33) CPEN Not Connected. VBUS Pull-up to 5 V. ID Not Connected.

4-Port USB 2.0 Hub

On the TEI0022 board there are up to four USB 2.0 Hi-Speed ports available. The USB 2.0 ports are provided by Microchip Cypress USB2514B 4-port USB 2.0 Hub controller (U33) which is connected to the USB PHY USB3320C (U8) connected to the Intel Cyclone V HPS via ULPI.

Buttons

There are four buttons present on the TEI0022 board. The following section describes the functionalities of the particular buttons. The final functionality is set by the management Intel MAX10.

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anchor Table_OBP_DIP_Buttons title Buttons functionality description
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Button Position ON Position OFF Notes S1 HPS_RST#_SW is high HPS_RST#_SW is low Reset (cold) the Intel Cyclone V HPS S3 HPS_WARM_RST#_SW is high HPS_WARM_RST#_SW is low Reset (warm) the Intel Cyclone V HPS S4 FPGA_RST#_SW is high FPGA_RST#_SW is low Reset the Intel Cyclone V FPGA S5 USER_BTN_SW is high USER_BTN_SW is low User button

DIP-Switches

There are three 4-bit DIP-switches present on the TEI0022 board to configure options and set parameters. The following section describes the functionalities of the particular switches.

DIP-switch S2

The table below describes the functionalities of the switches of DIP-switch S2 at their single positions:

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anchor Table_OBP_DIP_S2 title DIP-switch S2 functionality description
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true DIP-switch S2 Position ON Position OFF Notes S4-1 HPS_SW1 is low HPS_SW1 is high User switch S4-2 HPS_SW2 is low HPS_SW2 is high User switch S4-3 FPGA_SW1 is low FPGA_SW1 is high User switch S4-4 FPGA_SW2 is low FPGA_SW2 is high User switch

DIP-switch S7

The table below describes the functionalities of the switches of DIP-switch S7 at their single positions:

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anchor Table_OBP_DIP_S7 title DIP-switch S7 functionality description
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true DIP-switch S7 Position ON Position OFF Notes S7-1 HPS_SPI_SS/BOOTSEL0 is low HPS_SPI_SS/BOOTSEL0 is high Boot select S7-2 QSPI_CS/BOOTSEL1 is low QSPI_CS/BOOTSEL1 is high Boot select S7-3 JTAGSEL0 is low JTAGSEL0 is high JTAG select S7-4 JTAGSEL1 is low JTAGSEL1 is high JTAG select

DIP-switch S8

The table below describes the functionalities of the switches of DIP-switch S8 at their single positions:

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anchor Table_OBP_DIP_S8 title DIP-switch S8 functionality description
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true DIP-switch S8 Position ON Position OFF Notes S8-1 JTAGEN is high JTAGEN is low JTAG select S8-2 VID0_SW is low VID0_SW is high FMC_VADJ selection S8-3 VID1_SW is low VID1_SW is high FMC_VADJ selection S8-4 VID2_SW is low VID2_SW is high FMC_VADJ selection

On-board LEDs

The TEI0022 board is equipped with several LEDs to signal current states and activities. The functionality of the LEDs D11...14 are user LEDs. The LED D8 shows the Intel Cyclone V configuration progress. LEDs D15, D18...19 shows the UART connection and the other LEDs mentioned in the table are supply power status LEDs.

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anchor Table_OBP_LED title On-board LEDs
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Designator Color Connected to Active Level Note D11 Green Intel Cyclone V HPS L User LED D12 Green Intel Cyclone V HPS L User LED D13 Green Intel Cyclone V FPGA L User LED D14 Green Intel Cyclone V FPGA L User LED D8 Green Intel Cyclone V FPGA L Status: Configuration "Done" D15 Green FT234XD L UART D18 Green UART TX H UART D19 Green UART RX H UART D21 Green +12.0V H Status of +12.0V voltage rail D1 Green +12.0V_FMC H Status of +12.0V_FMC voltage rail D2 Green +5.0V H Status of +5.0V voltage rail D3 Green +3.3V H Status of +3.3V voltage rail D20 Green +3.3V_MAX10 H Status of +3.3V_MAX10 voltage rail D22 Green +3.3V_FMC H Status of +3.3V_FMC voltage rail D4 Green +2.5V H Status of +2.5V voltage rail D5 Green +1.8V H Status of +1.8V voltage rail D7 Green VCC H Status of VCC voltage rail D9 Green FMC_VADJ H Status of FMC_VADJ voltage rail D6 Green VDD_DDR_FPGA H Status of VDD_DDR_FPGA voltage rail D23 Green VDD_DDR_HPS H Status of VDD_DDR_HPS voltage rail D17 Green VTT_DDR_FPGA H Status of VTT_DDR_FPGA voltage rail D10 Green VTT_DDR_HPS H Status of VTT_DDR_HPS voltage rail

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• Part number: IS43TR16512BL-125KBLI
• Supply voltage: 1.35 V
• Speed: ???
• Temperature: TC = -40 °C up to 95 °C

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U1) is provided with Analog Devices ADIN1300. The Ethernet PHY RGMII interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V. The reference clock input of the PHY is supplied from the on-board 25.0 MHz oscillator (U2).

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anchor Table_OBP_ETH title Ethernet PHY to HPS connections
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Bank Signal Name ETH Signal Description 7B ETH_TXCK RGMII Transmit Reference Clock 7B ETH_TXD0 RGMII Transmit Data 0 7B ETH_TXD1 RGMII Transmit Data 1 7B ETH_TXD2 RGMII Transmit Data 2 7B ETH_TXD3 RGMII Transmit Data 3 7B ETH_TXCTL RGMII Transmit Control 7B ETH_RXCK RGMII Receive Reference Clock 7B ETH_RXD0 RGMII Receive Data 0 7B ETH_RXD1 RGMII Receive Data 2 7B ETH_RXD2 RGMII Receive Data 3 7B ETH_RXD3 RGMII Receive Data 4 7B ETH_RXCTL RGMII Receive Control 7C ETH_RST Reset 7B ETH_MDC Management Data Clock 7B ETH_MDIO Management Data I/O 7B PHY_INT Interrupt

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Oscillators

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anchor Table_OBP_CLK title Osillators
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Designator Description Frequency Note U2 Ethernet 25 MHz U37 FPGA 50 MHz Bank 5B and MAX10 U35 FPGA 50 MHz Bank 4A and 3B U44 HPS 25 MHz CLK1, CLK2 U32 FTDI 12 MHz U3 HDMI 12 MHz U34 USB 24 MHz HPS 25 MHz CLK1 HPS SOCKIT HPS 25 MHz CLK2 HPS SOCKIT FPGA 50 MHz Bank 3B SOCKIT FPGA 50 MHz Bank 4A SOCKIT FPGA 50 MHz Bank 5B SOCKIT FPGA 50 MHz Bank 8A SOCKIT FPGA 50 MHz Pin P8/9 SOCKIT

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