...
| Scroll Title |
|---|
| anchor | Table_SIP_FMC_Interfaces |
|---|
| title | FMC connector pin-outs of available interfaces |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Interface | I/O Signal Count | Pin schematic Names / FMC Pins | Connected to | Notes |
|---|
| JTAG | 5 | FMC_TCK, Pin J4-D29 FMC_TMS, Pin J4-D33 FMC_TDI, Pin J4-D30 FMC_TDO, Pin J4- D31 FMC_TRST#, Pin J4- D34 | Intel MAX10 U41, Bank 3 | VCCIO: +3.3V | | I2C | 2 | FMC_SCL, Pin J4-C30 FMC_SDA, Pin J4-C31 | Intel MAX10 U41, Bank 3 and Intel Cyclone V U10, Bank 7A | I2C-lines pulled-up to +3.3V | | Control Lines | 2 | FMC_PRSNT_M2C#, Pin J4-H2 (pulled-up to +3.3V) FMC_PG_C2M, Pin J4-D1 (pulled-up to +3.3V) | Intel MAX10 U41, Bank 3 and Intel Cyclone V U10, Bank 5B | 'PG' = 'Power Good'-signal 'C2M' = carrier to (Mezzanine) module 'M2C' = (Mezzanine) module to carrier |
|
Several VCCIO voltages are available on the FMC connector to operate the I/O's on different voltage levels:
| Scroll Title |
|---|
| anchor | Table_SIP_FMC_Voltage |
|---|
| title | Available VCCIO voltages on FMC connector |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| VCCIO Schematic Name | FMC Connector J4 Pins | Notes |
|---|
| +12.0V_FMC | C35/C37 | extern 12V power supply | | +3.3V_FMC | D36/D38/D40/C39 | 3.3V peripheral supply voltage | | +3.3V | D32 | 3.3V peripheral supply voltage | | FMC_VADJ | H40/G39 | adjustable FMC VCCIO voltage, supplied by DC-DC converter U43 | | FMC_VREF_A_M2C | H1 | adjustable reference voltage |
|
JTAG Interface
According to the JTAGEN and JTAGSEL[1..0] pins the management Intel MAX10, the Intel Cyclone V HPS, the Intel Cyclone V FPGA or the FMC can be accessed.
...
| Scroll Title |
|---|
| anchor | Table_OBP |
|---|
| title | On board peripherals |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Chip/Interface | Designator | Notes |
|---|
| Temperature Sensor | U16 |
| | QSPI | U6, U15 |
| | EEPROM | U38 |
| | LEDOn-Board LEDs | D1...15, D17...23 |
| | DDR3 SDRAM | U26...29 |
| | Gigabit Ethernet PHY | U1 |
| | Clock Sources | U... |
| | SwitchDIP-Switches | S2, S7...8 |
|
|
|
| | JTAG | U21 |
| | UART | U30 |
| | HDMI | U23 |
| | System Controller Intel MAX10 | U41 |
| | PMOD | P1...4 |
| | Power Monitoring | U54 |
| | High-Speed USB ULPI PHY | U8 |
| | 4-Port USB 2.0 Hub | U33 |
| | SD Card | J3 |
| | Intel Cyclone V | U10 |
|
|
...
| Scroll Title |
|---|
| anchor | Table_OBP_EEPROM |
|---|
| title | On-board configuration EEPROMs overview |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| EEPROM Model | I2C Address | Designator | Memory Density | Purpose | Notes |
|---|
| 24AA025E48T-I/OT | 0x50 | U38 | 2 KBit | Ethernet MAC |
| | 93AA56BT-I/OT | - | U31 | 2 KBit | JTAG Configuration |
|
|
High-
...
Speed USB ULPI PHY
USB PHY (U8) is provided by USB3320C from Microchip. The ULPI interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V and PHY reference clock input is supplied from the on-board 24.0 MHz oscillator (U34).
...
There are three 4-bit DIP-switches present on the TEI0022 board to configure options and set parameters. The following section describes the functionalities of the particular switches.
DIP-switch Switch S2
The table below describes the functionalities of the switches of DIP-switch S2 at their single positions:
| Scroll Title |
|---|
| anchor | Table_OBP_DIP_S2 |
|---|
| title | DIP-switch S2 functionality description |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| DIP-switch S2 | Position ON | Position OFF | Notes |
|---|
| S4-1 | HPS_SW1 is low | HPS_SW1 is high | User switch | | S4-2 | HPS_SW2 is low | HPS_SW2 is high | User switch | | S4-3 | FPGA_SW1 is low | FPGA_SW1 is high | User switch | | S4-4 | FPGA_SW2 is low | FPGA_SW2 is high | User switch |
|
DIP-switch Switch S7
The table below describes the functionalities of the switches of DIP-switch S7 at their single positions:
| Scroll Title |
|---|
| anchor | Table_OBP_DIP_S7 |
|---|
| title | DIP-switch S7 functionality description |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| DIP-switch S7 | Position ON | Position OFF | Notes |
|---|
| S7-1 | HPS_SPI_SS/BOOTSEL0 is low | HPS_SPI_SS/BOOTSEL0 is high | Boot select | | S7-2 | QSPI_CS/BOOTSEL1 is low | QSPI_CS/BOOTSEL1 is high | Boot select | | S7-3 | JTAGSEL0 is low | JTAGSEL0 is high | JTAG select | | S7-4 | JTAGSEL1 is low | JTAGSEL1 is high | JTAG select |
|
DIP-switch Switch S8
The table below describes the functionalities of the switches of DIP-switch S8 at their single positions:
| Scroll Title |
|---|
| anchor | Table_OBP_DIP_S8 |
|---|
| title | DIP-switch S8 functionality description |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| DIP-switch S8 | Position ON | Position OFF | Notes |
|---|
| S8-1 | JTAGEN is high | JTAGEN is low | JTAG select | | S8-2 | VID0_SW is low | VID0_SW is high | FMC_VADJ selection | | S8-3 | VID1_SW is low | VID1_SW is high | FMC_VADJ selection | | S8-4 | VID2_SW is low | VID2_SW is high | FMC_VADJ selection |
|
On-
...
Board LEDs
The TEI0022 board is equipped with several LEDs to signal current states and activities. The functionality of the LEDs D11...14 are user LEDs. The LED D8 shows the Intel Cyclone V configuration progress. LEDs D15, D18...19 shows the UART connection and the other LEDs mentioned in the table are supply power status LEDs.
...
| Scroll Title |
|---|
| anchor | Table_OBP_CLK |
|---|
| title | Osillators |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Designator | Description | Frequency | Note |
|---|
|
|
|
| | U37 | FPGA | 50 MHz | Bank 5B and MAX10 | | U35 | FPGA | 50 MHz | Bank 4A and 3B |
|
|
|
| | U44 | HPS, Ethernet | 25 MHz | HPS CLK1 |
| HPS |
| HPS CLK2 | | U32 | FTDI | 12 MHz |
| | U34 | USB HUB, PHY | 24 MHz |
|
|
|
|
|
|
|
|
|
| HPS | 25 MHz | CLK1 HPS SOCKIT |
| HPS | 25 MHz | CLK2 HPS SOCKIT |
| FPGA | 50 MHz | Bank 3B SOCKIT |
| FPGA | 50 MHz | Bank 4A SOCKIT |
| FPGA | 50 MHz | Bank 5B SOCKIT |
| FPGA | 50 MHz | Bank 8A SOCKIT |
| FPGA | 50 MHz | Pin P8/9 SOCKIT |
|
|
|
|
|
...
| Page properties |
|---|
|
In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
|
Power Supply
Power supply with minimum current capability of xx A for system startup is recommendedThe maximum power consumption of this board mainly depends on the design which is running on the FPGA. Intel provides a power estimator excel sheets to calculate power consumption.
Power Consumption
| Scroll Title |
|---|
| anchor | Table_PWR_PC |
|---|
| title | Power Consumption |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Power Input Pin | Typical Current |
|---|
| VIN+12.0V_IN | TBD* |
|
* TBD - To Be Determined
Power Distribution Dependencies
All on-board voltages of the TEI0022 are generated out of the extern applied 12 V power supply.
There are following dependencies how the initial 12V power supply is distributed to the on-board DC-DC converters, which power up further DCDC converters and the particular on-board voltages:
| Scroll Title |
|---|
| anchor | Figure_PWR_PD |
|---|
| title | Power Distribution |
|---|
|
| Scroll Ignore |
|---|
Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
| Scroll Only |
|---|
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
|
...