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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

...

Pmod Connector

The FMC (FPGA Mezzanine Card) connector J4 with low pin count (LPC) provides as an ANSI/VITA 57.1 standard a modular interface to the Intel Cyclone V FPGA and exposes numerous of its TEI0022 board offers four Pmod (2x6 pins, SMD) connectors which provides as a standard modular interface single ended I/O pins for use by other mezzanine modules and expansion cards.with extension modules.

Following table gives an overview of the Pmod connectors and the signals routed to the attached Intel Cyclone V U10:The connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.

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titleFMC Pmod connectors informationpin description

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FMC SignalIntel Cyclone V DirectionI/O Signal Count (Single Ended/Differential)Voltage LevelNotes
LA0...1RX4 / 2FMC_VADJLA3, LA5, LA7, ..., LA33RX32 / 16FMC_VADJLA2, LA4, LA6, ..., LA32TX32 / 16FMC_VADJCLK0...1RX4 / 2FMC_VADJ

The FMC connector provides further interfaces like JTAG and I²C interfaces:

...

anchorTable_SIP_FMC_Interfaces
titleFMC connector pin-outs of available interfaces

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FMC_TCK, Pin J4-D29

FMC_TMS, Pin J4-D33

FMC_TDI, Pin J4-D30

FMC_TDO, Pin J4- D31

FMC_TRST#, Pin J4- D34

...

FMC_SCL, Pin J4-C30

FMC_SDA, Pin J4-C31

...

FMC_PRSNT_M2C#, Pin J4-H2 (pulled-up to +3.3V)

FMC_PG_C2M, Pin J4-D1 (pulled-up to +3.3V)

...

'PG' = 'Power Good'-signal

'C2M' = carrier to (Mezzanine) module

'M2C' = (Mezzanine) module to carrier

Pmod Connector P1 PinSignal Schematic NameConnected toNotes
1P0_IO1Intel Cyclone V U10, Pin X
2P0_IO2Intel Cyclone V U10, Pin X
3P0_IO3Intel Cyclone V U10, Pin X
4P0_IO4Intel Cyclone V U10, Pin X
7P0_IO5Intel Cyclone V U10, Pin X
8P0_IO6Intel Cyclone V U10, Pin X
9P0_IO7Intel Cyclone V U10, Pin X
10P0_IO8Intel Cyclone V U10, Pin X
Pmod Connector P2 PinSignal Schematic NameConnected toNotes
1P1_IO1Intel Cyclone V U10, Pin X
2P1_IO2Intel Cyclone V U10, Pin X
3P1_IO3Intel Cyclone V U10, Pin X
4P1_IO4Intel Cyclone V U10, Pin X
7P1_IO5Intel Cyclone V U10, Pin X
8P1_IO6Intel Cyclone V U10, Pin X
9P1_IO7Intel Cyclone V U10, Pin X
10P1_IO8Intel Cyclone V U10, Pin X
Pmod Connector P3 PinSignal Schematic NameConnected toNotes
1P2_IO1Intel Cyclone V U10, Pin X
2P2_IO2Intel Cyclone V U10, Pin X
3P2_IO3Intel Cyclone V U10, Pin X
4P2_IO4Intel Cyclone V U10, Pin X
7P2_IO5Intel Cyclone V U10, Pin X
8P2_IO6Intel Cyclone V U10, Pin X
9P2_IO7Intel Cyclone V U10, Pin X
10P2_IO8Intel Cyclone V U10, Pin X
Pmod Connector P4 PinSignal Schematic NameConnected toNotes
1P3_IO1Intel Cyclone V U10, Pin X
2P3_IO2Intel Cyclone V U10, Pin X
3P3_IO3Intel Cyclone V U10, Pin X
4P3_IO4Intel Cyclone V U10, Pin X
7P3_IO5Intel Cyclone V U10, Pin X
8P3_IO6Intel Cyclone V U10, Pin X
9P3_IO7Intel Cyclone V U10, Pin X
10P3_IO8Intel Cyclone V U10, Pin X


FMC LPC Connector

The FMC (FPGA Mezzanine Card) connector J4 with low pin count (LPC) provides as an ANSI/VITA 57.1 standard a modular interface to the Intel Cyclone V FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.

The connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.

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titleFMC connectors information

Several VCCIO voltages are available on the FMC connector to operate the I/O's on different voltage levels:

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anchorTable_SIP_FMC_Voltage
titleAvailable VCCIO voltages on FMC connector

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JTAG Interface

According to the JTAGEN and JTAGSEL[1..0] pins the management Intel MAX10, the Intel Cyclone V HPS, the Intel Cyclone V FPGA or the FMC can be accessed.

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JTAGSEL1

JTAGSEL0

JTAGSEL1

JTAGSEL0
XXONIntel MAX10
ONONOFFIntel Cyclone V HPS
ONOFFOFFIntel Cyclone V FPGA
OFFONOFFFMC

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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anchorTable_OBP
titleOn board peripherals

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FMC SignalIntel Cyclone V DirectionI/O Signal Count (Single Ended/Differential)Voltage LevelNotes
LA0...1RX4 / 2FMC_VADJ
LA3, LA5, LA7, ..., LA33RX32 / 16FMC_VADJ
LA2, LA4, LA6, ..., LA32TX32 / 16FMC_VADJ
CLK0...1RX4 / 2FMC_VADJ


The FMC connector provides further interfaces like JTAG and I²C interfaces:

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InterfaceI/O Signal CountPin schematic Names / FMC PinsConnected toNotes
JTAG5

FMC_TCK, Pin J4-D29

FMC_TMS, Pin J4-D33

FMC_TDI, Pin J4-D30

FMC_TDO, Pin J4- D31

FMC_TRST#, Pin J4- D34

Intel MAX10 U41, Bank 3VCCIO: +3.3V
I2C2

FMC_SCL, Pin J4-C30

FMC_SDA, Pin J4-C31

Intel MAX10 U41, Bank 3 and Intel Cyclone V U10, Bank 7AI2C-lines pulled-up to +3.3V
Control Lines2

FMC_PRSNT_M2C#, Pin J4-H2 (pulled-up to +3.3V)

FMC_PG_C2M, Pin J4-D1 (pulled-up to +3.3V)

Intel MAX10 U41, Bank 3 and Intel Cyclone V U10, Bank 5B

'PG' = 'Power Good'-signal

'C2M' = carrier to (Mezzanine) module

'M2C' = (Mezzanine) module to carrier


Several VCCIO voltages are available on the FMC connector to operate the I/O's on different voltage levels:

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VCCIO Schematic NameFMC Connector J4 PinsNotes
+12.0V_FMCC35/C37extern 12V power supply
+3.3V_FMCD36/D38/D40/C393.3V peripheral supply voltage
+3.3VD323.3V peripheral supply voltage
FMC_VADJH40/G39adjustable FMC VCCIO voltage, supplied by DC-DC converter U43
FMC_VREF_A_M2CH1adjustable reference voltage


JTAG Interface

According to the JTAGEN and JTAGSEL[1..0] pins the management Intel MAX10 U41, the Intel Cyclone V HPS (U10), the Intel Cyclone V FPGA (U10) or the FMC (J4) can be accessed via the micro USB B connector J13.

...

Temperatur Sensor

The temperature sensor ADT7410 is implemented on the TEI0022 board.

Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

Two 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron MT25QL256ABA8E12, U6, U15) are provided for FPGA and HPS configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA and the HPS allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

Quad SPI Flash memory U6 is connected to the HPS bank 7B and U15 to FPGA bank 3A.

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titleHPS Quad SPI interface signals and connectionsJTAG pins connection

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JTAGSEL1

Signal NameQSPI Flash Memory U6 PinFPGA Pin
QSPI_CS/BOOTSEL1S#, Pin C2Bank 7B, Pin A18
QSPI_CLKC, Pin B2Bank 7B, Pin D19
QSPI_DATA0DQ0, Pin D3Bank 7B, Pin C20
QSPI_DATA1DQ1, Pin D2Bank 7B, Pin H18
QSPI_DATA2DQ2, Pin C4Bank 7B, Pin A19
QSPI_DATA3DQ3, Pin D4Bank 7B, Pin E19
QSPI_RSTRST#, Pin A4Bank 7A, Pin E24
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JTAGSEL0

JTAGSEL1

JTAGSEL0
XXONIntel MAX10
ONONOFFIntel Cyclone V HPS
ONOFFOFFIntel Cyclone V FPGA
OFFONOFFFMC


FAN Connector

The TEI0022 board offers one FAN connector for cooling the FPGA device. Depending on the assembly 5 V or 12 V are usable.

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titleFAN connectors
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titleFPGA Quad SPI interface signals and connections

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Connector

Signal
Name
QSPI Flash Memory U15 PinFPGA Pin
nCSOS#, Pin C2Bank 3A, Pin AB8
AS_DCKC, Pin B2Bank 3A, Pin U7
AS_DATA0DQ0, Pin D3Bank 3A, Pin AE6
AS_DATA1DQ1, Pin D2Bank 3A, Pin AE5
AS_DATA2DQ2, Pin C4Bank 3A, Pin AE8
AS_DATA3DQ3, Pin D4Bank 3A, Pin AC7
AS_RSTRST#, Pin A4Bank 7A, Pin B22

Programmable Clock Generator

There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U3) to generate various reference clocks for the module.

Schematic Names

Connected to

Notes
2-Pin FAN Connector J16, 5 V or 12 V power supply depending on R270/271 with BTS4141N High Side Switch

FAN_EN,

(High Side Switch U55, Pin 3)

Intel MAX10 U41, Pin C1Intel Cyclone V cooling FAN


SMA Connector

The TEI0022 board offers four SMA connector for trigger and clock input and output connected to the Intel Cyclone V.

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titleSMA connectors

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titleProgrammable quad PLL clock generator inputs and outputs

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Si5338A Pin

SMA Connector

Signal
Name / Description
Schematic Names

Connected to

Direction

Notes

IN1

-

Not ConnectedInput

Not used

IN2-GNDInputNot used

IN3

Reference input clock

U48, Pin 3Input25.000000 MHz oscillator U48, SiT8208

IN4

-GNDInputI2C slave device address LSB

IN5

-

Not ConnectedInputNot used
IN6-GNDInputNot used
SCLHPS_I2C_SCLHPS I2C Bus U10, Pin H23Input

I²C interface muxed to FPGA

Slave address: 0x70.

SDAHPS_I2C_SDAHPS I2C Bus U10, Pin A25Input / Output

I²C interface muxed to FPGA

Slave address: 0x70.

CLK0A/B

CLK_B3B_p/n

U10, Pin AF14/15Output

Clock to FPGA bank 3B

CLK1A/B

CLK_B4A_p/n

U10, Pin AA16/AB17Output

Clock to FPGA bank 4A

CLK2ACLK_50MHz_MAX10U41, Pin H6Output

Clock to Intel MAX10 bank 2

CLK2BHPS_CLK2_25MHzU10, Pin F25OutputClock to HPS bank 7A
CLK3A/BCLK_B5B_p/nU10, Pin Y26/27OutputClock to HPS bank 5B

Oscillators

The FPGA module has following reference clocking source provided by an on-board oscillator:

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anchorTable_OBP_OSC
titleReference clock signals

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J7EXT_CLK_INPUTIntel Cyclone V U10, Pin AA26
J8CLK_INPUTIntel Cyclone V U10, Pin AB27
J9TRIGGER_INPUTIntel Cyclone V U10, Pin AE29
J10TRIGGER_OUTPUTIntel Cyclone V U10, Pin AD29


SD Card Connector

SD Card connector J3 is connected to the Intel Cyclone V.

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Page properties
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


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titleOn board peripherals

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Chip/InterfaceDesignatorNotes
Temperature SensorU16
QSPIU6, U15
EEPROMU38
On-Board LEDsD1...15, D17...23
DDR3 SDRAMU26...29
Gigabit Ethernet PHYU1
Clock SourcesU...
DIP-SwitchesS2, S7...8
Programmable Clock Generator

JTAGU21
UARTU30
HDMIU23
System Controller Intel MAX10U41
PMODP1...4
Power MonitoringU54
High-Speed USB ULPI PHYU8
4-Port USB 2.0 HubU33
SD CardJ3
Intel Cyclone VU10


Temperatur Sensor

The temperature sensor ADT7410 is implemented on the TEI0022 board.

UART Interface

A UART connection between the USB B connector J5 and the Intel Cyclone HPS U10 is possible via the FT234XD (U30) chip.

Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

Two 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron MT25QL256ABA8E12, U6, U15) are provided for FPGA and HPS configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA and the HPS allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

Quad SPI Flash memory U6 is connected to the HPS bank 7B and U15 to FPGA bank 3A.

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titleHPS Quad SPI interface signals and connections

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Signal NameQSPI Flash Memory U6 PinFPGA Pin
QSPI_CS/BOOTSEL1S#, Pin C2Bank 7B, Pin A18
QSPI_CLKC, Pin B2Bank 7B, Pin D19
QSPI_DATA0DQ0, Pin D3Bank 7B, Pin C20
QSPI_DATA1DQ1, Pin D2Bank 7B, Pin H18
QSPI_DATA2DQ2, Pin C4Bank 7B, Pin A19
QSPI_DATA3DQ3, Pin D4Bank 7B, Pin E19
QSPI_RSTRST#, Pin A4Bank 7A, Pin E24



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Signal NameQSPI Flash Memory U15 PinFPGA Pin
nCSOS#, Pin C2Bank 3A, Pin AB8
AS_DCKC, Pin B2Bank 3A, Pin U7
AS_DATA0DQ0, Pin D3Bank 3A, Pin AE6
AS_DATA1DQ1, Pin D2Bank 3A, Pin AE5
AS_DATA2DQ2, Pin C4Bank 3A, Pin AE8
AS_DATA3DQ3, Pin D4Bank 3A, Pin AC7
AS_RSTRST#, Pin A4Bank 7A, Pin B22


Intel Cyclone V

The on TEI0022 board used Intel Cyclone V device is a SoC with integrated Arm-based HPS. The 5CSEMA5F31C8N version delivers one hard memory controller, 80K logic elements in an FineLineBGA (FBGA) with 896 pins for the commercial temperature range of TJ = 0...85 °C with speed grade eight.

Programmable Clock Generator

There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U3) to generate various reference clocks for the module.

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Si5338A PinSignal Name / DescriptionConnected toDirectionNotes

IN1

-

Not ConnectedInput

Not used

IN2-GNDInputNot used

IN3

Reference input clock

U48, Pin 3Input25.000000 MHz oscillator U48, SiT8208

IN4

-GNDInputI2C slave device address LSB

IN5

-

Not ConnectedInputNot used
IN6-GNDInputNot used
SCLHPS_I2C_SCLHPS I2C Bus U10, Pin H23Input

I²C interface muxed to FPGA

Slave address: 0x70.

SDAHPS_I2C_SDAHPS I2C Bus U10, Pin A25Input / Output

I²C interface muxed to FPGA

Slave address: 0x70.

CLK0A/B

CLK_B3B_p/n

U10, Pin AF14/15Output

Clock to FPGA bank 3B

CLK1A/B

CLK_B4A_p/n

U10, Pin AA16/AB17Output

Clock to FPGA bank 4A

CLK2ACLK_50MHz_MAX10U41, Pin H6Output

Clock to Intel MAX10 bank 2

CLK2BHPS_CLK2_25MHzU10, Pin F25OutputClock to HPS bank 7A
CLK3A/BCLK_B5B_p/nU10, Pin Y26/27OutputClock to HPS bank 5B


Oscillators

The FPGA module has following reference clocking source provided by an on-board oscillator:

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Clock SourceFrequencySignal Schematic NameClock DestinationNotes
U48, SiT8208AI


25.0 MHz


CLK_25MHz_R

Si5338A PLL U3, Pin 3 (IN3)
HPS_CLK1_25MHzHPS Bank 7A U10, Pin D25
ETH_XTAL_INETH PHY U1, Pin 9
U32, SiT8208AI12.0 MHzOSCIFT2232H U21, Pin 3
U34, SiT8008BI24.0 MHzUSB_CLK24_HUBUSB Hub U33, Pin 33


USB_CLK24_PHYUSB PHY U8, Pin 26


I2C

The TEI0022 provides two independent I2C busses. One bus is used to connect the FMC I2C with the Intel Cyclone V HPS. The other bus is used to handle the on-board I2C devices.

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BusI2C DeviceDesignatorI2C AddressSchematic Names of I2C Bus LinesNotes
HPS I2CTemperature Sensor0x4AU16HPS_I2C_SCL / HPS_I2C_SDA3.3 V reference voltage
HPS I2CEEPROM0x50U38HPS_I2C_SCL / HPS_I2C_SDA3.3 V reference voltage
HPS I2CHDMI0x72U23HPS_I2C_SCL / HPS_I2C_SDA3.3 V reference voltage
HPS FMC I2CFMC0x50J4FMC_SCL / FMC_SDA3.3 V reference voltage


System Controller Intel MAX10

The TEI0022 is equipped with an Intel MAX10 (U41) which is the central system management unit where essential control signals are logically linked by the implemented logic of the FPGA firmware. This generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and buttons between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller. Other tasks of the System Controller are the monitoring of the power-on sequence and configuration of the Intel Cyclone V FPGA. The functionalities and configuration of the pins depend on its firmware.

EEPROM

The TEI0022 board contains two EEPROMs for configuration and general user purposes.

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EEPROM ModelI2C AddressDesignatorMemory DensityPurposeNotes
24AA025E48T-I/OT0x50U382 KBitEthernet MAC
93AA56BT-I/OT-U312 KBitJTAG Configuration


High-Speed USB ULPI PHY

USB PHY (U8) is provided by USB3320C from Microchip. The ULPI interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V and PHY reference clock input is supplied from the on-board 24.0 MHz oscillator (U34).

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I2C

The TEI0022 provides two independent I2C busses. One bus is used to connect the FMC I2C with the Intel Cyclone V HPS. The other bus is used to handle the on-board I2C devices.

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BusI2C DeviceDesignatorI2C AddressSchematic Names of I2C Bus LinesNotes
HPS I2CTemperature Sensor0x4AU16HPS_I2C_SCL / HPS_I2C_SDA3.3 V reference voltage
HPS I2CEEPROM0x50U38HPS_I2C_SCL / HPS_I2C_SDA3.3 V reference voltage
HPS I2CHDMI0x72U23HPS_I2C_SCL / HPS_I2C_SDA3.3 V reference voltage
HPS FMC I2CFMC0x50J4FMC_SCL / FMC_SDA3.3 V reference voltage

System Controller Intel MAX10

The TEI0022 is equipped with an Intel MAX10 (U41) which is the central system management unit where essential control signals are logically linked by the implemented logic of the FPGA firmware. This generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and buttons between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller. Other tasks of the System Controller are the monitoring of the power-on sequence and configuration of the Intel Cyclone V FPGA. The functionalities and configuration of the pins depend on its firmware.

EEPROM

PHY PinConnected toNotes
ULPIIntel Cyclone V HPS (U10)
REFCLK24 MHz from on board oscillator (U34)
REFSEL[0..2]High (3.3 V)
RESETBIntel Cyclone V HPS (U10)
DP, DM4-port USB 2.0 Hub (U33)
CPENNot Connected.
VBUSPull-up to 5 V.
IDNot Connected.


4-Port USB 2.0 Hub

On the TEI0022 board there are up to four USB 2.0 Hi-Speed ports available (J2, J12). The USB 2.0 ports are provided by Microchip Cypress USB2514B 4-port USB 2.0 Hub controller (U33) which is connected to the USB PHY USB3320C (U8) connected to the Intel Cyclone V HPS via ULPI.

Buttons

There are four buttons present on the TEI0022 board. The following section describes the functionalities of the particular buttons. The final functionality is set by the management Intel MAX10The TEI0022 board contains two EEPROMs for configuration and general user purposes.

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EEPROM ModelI2C AddressDesignatorMemory DensityPurposeNotes
24AA025E48T-I/OT0x50U382 KBitEthernet MAC93AA56BT-I/OT-U312 KBitJTAG Configuration

High-Speed USB ULPI PHY

ButtonPosition ONPosition OFFNotes
S1HPS_RST#_SW is highHPS_RST#_SW is lowReset (cold) the Intel Cyclone V HPS
S3HPS_WARM_RST#_SW is highHPS_WARM_RST#_SW is lowReset (warm) the Intel Cyclone V HPS
S4FPGA_RST#_SW is highFPGA_RST#_SW is lowReset the Intel Cyclone V FPGA
S5USER_BTN_SW is highUSER_BTN_SW is lowUser button


DIP-Switches

There are three 4-bit DIP-switches present on the TEI0022 board to configure options and set parameters. The following section describes the functionalities of the particular switches.

DIP-Switch S2

The table below describes the functionalities of the switches of DIP-switch S2 at their single positions:USB PHY (U8) is provided by USB3320C from Microchip. The ULPI interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V and PHY reference clock input is supplied from the on-board 24.0 MHz oscillator (U34).

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titleUSB PHY interface connectionsDIP-switch S2 functionality description

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PHY PinConnected toNotes
ULPIIntel Cyclone V HPS (U10)REFCLK24 MHz from on board oscillator (U34)REFSEL[0..2]High (3.3 V)RESETBIntel Cyclone V HPS (U10)DP, DM4-port USB 2.0 Hub (U33)CPENNot Connected.VBUSPull-up to 5 V.IDNot Connected.

4-Port USB 2.0 Hub

On the TEI0022 board there are up to four USB 2.0 Hi-Speed ports available. The USB 2.0 ports are provided by Microchip Cypress USB2514B 4-port USB 2.0 Hub controller (U33) which is connected to the USB PHY USB3320C (U8) connected to the Intel Cyclone V HPS via ULPI.

Buttons

DIP-switch S2Position ONPosition OFFNotes
S4-1HPS_SW1 is lowHPS_SW1 is highUser switch
S4-2HPS_SW2 is lowHPS_SW2 is highUser switch
S4-3FPGA_SW1 is lowFPGA_SW1 is highUser switch
S4-4FPGA_SW2 is lowFPGA_SW2 is highUser switch


DIP-Switch S7

The table below describes the functionalities of the switches of DIP-switch S7 at their single positions:There are four buttons present on the TEI0022 board. The following section describes the functionalities of the particular buttons. The final functionality is set by the management Intel MAX10.

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Button
DIP-switch S7Position ONPosition OFFNotes
S1
S7-1HPS_
RST#_SW is high
HPS_RST#_SW is lowReset (cold) the Intel Cyclone V HPS
S3HPS_WARM_RST#_SW is highHPS_WARM_RST#_SW is lowReset (warm) the Intel Cyclone V HPS
S4FPGA_RST#_SW is highFPGA_RST#_SW is lowReset the Intel Cyclone V FPGA
S5USER_BTN_SW is highUSER_BTN_SW is lowUser button

DIP-Switches

There are three 4-bit DIP-switches present on the TEI0022 board to configure options and set parameters. The following section describes the functionalities of the particular switches.

SPI_SS/BOOTSEL0 is lowHPS_SPI_SS/BOOTSEL0 is highBoot select
S7-2QSPI_CS/BOOTSEL1 is lowQSPI_CS/BOOTSEL1 is highBoot select
S7-3JTAGSEL0 is lowJTAGSEL0 is highJTAG select
S7-4JTAGSEL1 is lowJTAGSEL1 is highJTAG select


DIP-Switch S8DIP-Switch S2

The table below describes the functionalities of the switches of DIP-switch S2 S8 at their single positions:

S4
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DIP-switch
S2
S8Position ONPosition OFFNotes
S4
S8-1
HPS_SW1
JTAGEN is
low
high
HPS_SW1
JTAGEN is
high
low
User switch
JTAG select
S4
S8-2
HPS
VID0_
SW2
SW is low
HPS
VID0_
SW2
SW is high
User switch
FMC_VADJ selection
S8-3
FPGA
VID1_
SW1
SW is low
FPGA
VID1_
SW1
SW is high
User switchS4
FMC_VADJ selection
S8-4
FPGA
VID2_
SW2
SW is low
FPGA
VID2_
SW2
SW is high
User switch

DIP-Switch S7

FMC_VADJ selection


On-Board LEDs

The TEI0022 board is equipped with several LEDs to signal current states and activities. The functionality of the LEDs D11...14 are user LEDs. The LED D8 shows the Intel Cyclone V configuration progress. LEDs D15, D18...19 shows the UART connection and the other LEDs mentioned in the table are supply power status LEDs.The table below describes the functionalities of the switches of DIP-switch S7 at their single positions:

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titleDIP-switch S7 functionality descriptionOn-board LEDs

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DIP-switch S7Position ONPosition OFFNotes
S7-1HPS_SPI_SS/BOOTSEL0 is lowHPS_SPI_SS/BOOTSEL0 is highBoot select
S7-2QSPI_CS/BOOTSEL1 is lowQSPI_CS/BOOTSEL1 is highBoot select
S7-3JTAGSEL0 is lowJTAGSEL0 is highJTAG select
S7-4JTAGSEL1 is lowJTAGSEL1 is highJTAG select

DIP-Switch S8

The table below describes the functionalities of the switches of DIP-switch S8 at their single positions:

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DesignatorColorConnected toActive LevelNote
D11GreenIntel Cyclone V HPSLUser LED
D12GreenIntel Cyclone V HPSLUser LED
D13GreenIntel Cyclone V FPGALUser LED
D14GreenIntel Cyclone V FPGALUser LED
D8GreenIntel Cyclone V FPGALStatus: Configuration "Done"
D15GreenFT234XDLUART
D18GreenUART TXHUART
D19GreenUART RXHUART
D21Green+12.0VHStatus of +12.0V voltage rail
D1Green+12.0V_FMCHStatus of +12.0V_FMC voltage rail
D2Green+5.0VHStatus of +5.0V voltage rail
D3Green+3.3VHStatus of +3.3V voltage rail
D20Green+3.3V_MAX10HStatus of +3.3V_MAX10 voltage rail
D22Green+3.3V_FMCHStatus of +3.3V_FMC voltage rail
D4Green+2.5VHStatus of +2.5V voltage rail
D5Green+1.8VHStatus of +1.8V voltage rail
D7GreenVCCHStatus of VCC voltage rail
D9GreenFMC_VADJHStatus of FMC_VADJ voltage rail
D6GreenVDD_DDR_FPGAHStatus of VDD_DDR_FPGA voltage rail
D23GreenVDD_DDR_HPSHStatus of VDD_DDR_HPS voltage rail
D17GreenVTT_DDR_FPGAHStatus of VTT_DDR_FPGA voltage rail
D10GreenVTT_DDR_HPSHStatus of VTT_DDR_HPS voltage rail
D25GreenIntel Cyclone V HPS U10, Pin B23LStatus of the daughterboard identification


DDR3 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TEI0022 SoM has one GByte volatile DDR3 SDRAM memory per FPGA (U26, U27) and HPS (U28, U29) for storing user application code and data.

  • Part number: IS43TR16512BL-125KBLI
  • Supply voltage: 1.35 V
  • Speed: ???
  • Temperature: TC = -40 °C up to 95 °C

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U1) is provided with Analog Devices ADIN1300. The Ethernet PHY RGMII interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V. The reference clock input of the PHY is supplied from the on-board 25.0 MHz oscillator (U48).

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titleEthernet PHY to HPS connections

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BankSignal NameETHSignal Description
7BETH_TXCK
RGMII Transmit Reference Clock
7BETH_TXD0
RGMII Transmit Data 0
7BETH_TXD1
RGMII Transmit Data 1
7BETH_TXD2
RGMII Transmit Data 2
7BETH_TXD3
RGMII Transmit Data 3
7B

ETH_TXCTL


RGMII Transmit Control
7BETH_RXCK
RGMII Receive Reference Clock
7BETH_RXD0
RGMII Receive Data 0
7BETH_RXD1
RGMII Receive Data 2
7BETH_RXD2
RGMII Receive Data 3
7BETH_RXD3
RGMII Receive Data 4
7B

ETH_RXCTL


RGMII Receive Control
7CETH_RST
Reset
7BETH_MDC
Management Data Clock
7BETH_MDIO
Management Data I/O
7BPHY_INT
Interrupt


HDMI Connector

The TEI0022 board provides an HDMI interface routed to the Intel Cyclone FPGA (U10). The HDMI interface is created by the HDMI transmitter ADV7511 provided by Analog Devices. The HDMI transmitter is incorporated in conjunction with the HDMI protection circuit TI TPD12S016 for more signal robustness.

On-Board LEDs

The TEI0022 board is equipped with several LEDs to signal current states and activities. The functionality of the LEDs D11...14 are user LEDs. The LED D8 shows the Intel Cyclone V configuration progress. LEDs D15, D18...19 shows the UART connection and the other LEDs mentioned in the table are supply power status LEDs.

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DDR3 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TEI0022 SoM has one GByte volatile DDR3 SDRAM memory per FPGA and HPS for storing user application code and data.

  • Part number: IS43TR16512BL-125KBLI
  • Supply voltage: 1.35 V
  • Speed: ???
  • Temperature: TC = -40 °C up to 95 °C

Gigabit Ethernet PHY

On-board Gigabit Ethernet PHY (U1) is provided with Analog Devices ADIN1300. The Ethernet PHY RGMII interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V. The reference clock input of the PHY is supplied from the on-board 25.0 MHz oscillator (U2).

Interrupt
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titleEthernet PHY to HPS connectionsHDMI connector signals and pins

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HDMI connector J11Signal Schematic NameConnected toNotes
Pin 1, 3HDMI_TX2_P / HDMI_TX2_NHDMI transmitter, Pin 43, 42also connected to HDMI protection circuit
Pin 4, 6HDMI_TX1_P / HDMI_TX1_N

HDMI transmitter, Pin 40, 39

also connected to HDMI protection circuit

Pin 7, 9HDMI_TX0_P / HDMI_TX0_NHDMI transmitter, Pin 36, 35also connected to HDMI protection circuit
Pin 10, 12HDMI_TXC_P / HDMI_TXC_NHDMI transmitter, Pin 33, 32also connected to HDMI protection circuit
Pin 13CEC_BHDMI transmitter, Pin 48HDMI CEC, wired through HDMI protection circuit
Pin 15SCL_BHDMI transmitter, Pin 53HDMI I²C clock line, wired through HDMI protection circuit
Pin 16SDA_BHDMI transmitter, Pin 54HDMI I²C data line, wired through HDMI protection circuit
Pin 19HPD_BHDMI transmitter, Pin 30Hot Plug Detect, wired through HDMI protection circuit
Pin 185V_HDMIHDMI protection circuit, Pin 135V supply voltage, wired through HDMI protection circuit
BankSignal NameETHSignal Description
7BETH_TXCKRGMII Transmit Reference Clock7BETH_TXD0RGMII Transmit Data 07BETH_TXD1RGMII Transmit Data 17BETH_TXD2RGMII Transmit Data 27BETH_TXD3RGMII Transmit Data 37B

ETH_TXCTL

RGMII Transmit Control7BETH_RXCKRGMII Receive Reference Clock7BETH_RXD0RGMII Receive Data 07BETH_RXD1RGMII Receive Data 27BETH_RXD2RGMII Receive Data 37BETH_RXD3RGMII Receive Data 47B

ETH_RXCTL

RGMII Receive Control7CETH_RSTReset7BETH_MDCManagement Data Clock7BETH_MDIOManagement Data I/O7BPHY_INT



Oscillators

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DesignatorDescriptionFrequencyNote
















U37FPGA50 MHzBank 5B and MAX10
U35FPGA50 MHzBank 4A and 3B




U44HPS, Ethernet25 MHzHPS CLK1

HPS
HPS CLK2
U32FTDI12 MHz
U34USB HUB, PHY24 MHz











HPS25 MHzCLK1 HPS SOCKIT

HPS25 MHzCLK2 HPS SOCKIT

FPGA50 MHzBank 3B SOCKIT

FPGA50 MHzBank 4A SOCKIT

FPGA50 MHzBank 5B SOCKIT

FPGA50 MHzBank 8A SOCKIT

FPGA50 MHzPin P8/9 SOCKIT





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Voltage Monitor Circuit

The voltages +3.3V, +5.0V, and VCC are monitored by the voltage monitor circuit LTC2911 (U54), which generates the a reset signal at power-on. A manual reset is also possible as described in the

reset table.

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titleVoltage Monitor Circuit


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