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Scroll Title
anchorTable_SIP_B2B
titleGeneral PL I/O to B2B connectors information

Scroll Table Layout
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sortDirectionASC
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B2B ConnectorInterfacesNumber of I/ONotes
J1

User I/O

46 Single Ended, 23 Differential

16 Single Ended, 8 Differential

16 Single Ended, 8 Differential

16 Single Ended, 8 Differential

4 Single Ended

IOs are Loop-Back

IOs are Loop-Back

IOs are Loop-Back

IOs are Loop-Back

Connected to Module FPGA, Bank 66

Connected to Module FPGA, Bank 228

Connected to Module FPGA, Bank 229

Connected to Module FPGA, Bank 230

PL_1V8

J2

User IO

28 Single Ended, 14 Differential

6 Single Ended, 3 Differential

IOs are Loop-Back

IOs are Loop-Back

Connected to  Module FPGA, Bank 505

Connected to Module FPGA, Bank 128

Boot Mode 4 Single EndedMODE0...3
Control Signals25 Single Ended

PLL_SEL0, PLL_SEL1, PLL_RST, EN_GTR, EN_PL, PLL_LOLN, EN_PSGT, ERR_STATUS, ERR_OUT,SRST_B, INIT_B, PROG_B, EN_FPD , EN_LPD , DONE, EN_PLL_PWR, PLL_FINC ,PG_PLL_1V8, LP_GOOD, PG_DDR, PG_PL, PG_FPD, PG_PSGT, PG_GT_R, PG_GT_L

JTAG Interface7 Single EndedTCK, TDI, TMS, TDO, MR, Rxd, Txd
I22 Single EndedPLL_SCL, PLL_SDA
Clock

6 Single Ended, 3 Differential

CLK0, CLK7, CLK8

J3



User IO

24 Single Ended, 12 Differential

24 Single Ended, 12 Differential

Connected to Module FPGA, Bank 48

Connected to Module FPGA, Bank 47

Clock6 Single Ended, 3 DifferentialCLK228, CLK229, CLK230
PJTAG Interface7 Single EndedPJTAG0_TCK, PJTAG0_TDI, PJTAG0_TMS, PJTAG0_TDO,
MIO45 Single EndedMIO13..77
UART2 Single EndedTXD, RXD
Power Control Signals4 Single EndedPS_1V8, SI_PLL_1V8, VCCO_48, VCCO_47, PLL_3V3
J4User I/O

48 Single Ended, 24 Differential

48 Single Ended, 24 Differential

4 Single Ended

4 Single Ended

IOs are Loop-Back

IOs are Loop-Back

Connected to Module FPGA, Bank 64

Connected to Module FPGA, Bank 65

B64_T0...3

B65_T0...3

Power pins4 Single EndedVCCO_64, VCCO65


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