Page History

...

...

The Trenz Electronic TE0821 -01-3BI21FA is a powerful 4 x 5 cm MPSoC module integrated with a Xilinx Zynq UltraScale+ ZU3EGMPSoC. In addition, the module is equipped with a 2 2x 1 GB DDR4 SDRAM chip, 4Gb up to 128 Gb eMMC chip,  2x 64 MB flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages. . The module is equipped with a Lattice Mach XO2 CPLD for system controlling. 3x Robust high-speed connectors provide a large number of inputs and outputs.This module is pin compatible with Trenz Electronic TE0820 MPSoC modules (JM2 pin 100 is not connected).

The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.

All components cover at least the industrial temperature range from -40 ° C to + 85 ° C. The temperature range in which the module can be used depends on the customer design and the selected cooling. Please contact us for special solutions.

...

• SoC/FPGA
  
  • Package: SFVC784
  • Device: ZU2 ...ZU5, *
  • Engine:  EG, CG, EV, *
  • Speed: -1, -1L, -2, -2L, 3, *, **
  • Temperature: I, E, *, **Xilinx Zynq UltraScale+ XCZU3EG-1SFVC784I
    
  • ZU3EG, 784 Pin Packages
  • Application Processor: Quad-Core ARM Cortex-A53 MPCore
  • Real-Time Processor: Dual-core ARM Cortex-R5 MPCore
  Graphics Processor: Mali-400 MP2
• RAM/Storage
  • 2 GByte 2x  DDR4 SDRAM, 32-Bit databus-width
  • 128 MByte QSPI boot Flash in dual parallel mode
  • • Data Width: 16 Bit
    • Size: 8 Gb, *
    • Speed: 2400 Mbps, ***
  • 2x QSPI boot Flash in dual parallel mode
    • Data Width: 8 Bit
    • Size: 512 Mb Gb, *
  • 1x e.MMC Memory
    • Data Width: 16 Bit
    • Size: 8 Gb, *
    8 GByte e.MMC Memory (up to 64 GByte)
  • MAC address serial EEPROM with EUI-48 node identity
• On Board
  
  • Graphic Processing Unit (GPU) :Mali-400 MP2
  • Lattice MachXO2 CPLD
  • Programmable Clock Generator
  • Hi-speed USB2 ULPI Transceiver
  • 4x LEDS
• Interface
  • 1 Gbps RGMII Ethernet interface
  • Hi-speed USB2 ULPI transceiver with full OTG support
  • Graphic Processor Mali-400 MP2, *
  • 156 x High Performance (HP) und 96 x High Density PL I/Os
  • 4 x serial PS GTR transceivers
    • PCI Express interface
  Interface
  • PCI Express interface version 2.1 compliant
    • SATA 3.1
    specification compliant
    • interface

    • DisplayPort

    source-only

    • interface with video resolution up to 4k x 2k

    • 2x USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
  • 1 GB/s serial GMII interface
  • Hi-speed USB2 ULPI transceiver with full OTG support
  • 34 x High Performance und 96 x High Density PL I/Os
  • 14 x PS MIOs (6 of the MIOs intended for SD card interface in default configuration)
• Power
  • All power regulators on board
• Dimension
  • 40 x 50 mm
• Note
  • * depends on assembly version
  • ** also non low power assembly options possible
  • *** depends on used U+ Zynq and DDR4 combination4 x serial PS GTR transceivers
  • Rugged for shock and high vibration
• Power
  • All power supplies on board
• Dimension
  • 40 x 50 mm

Block Diagram

...

Main Components

...

1. Xilinx Zynq ZYNQ UltraScale+ XCZU3EGMPSoC, U1
2. Red LED (ERR_OUT), D3
3. Green LED (ERR_STATUS), D4
4. Red LED (DONE), D1
5. 10/100/1000 Mbps energy efficient ethernet transceiverEnergy Efficient Ethernet Transceiver, U8
6. 8Gb DDR4, U2-U3
7. 512 Mbit QSPI flash memory, U7-U17
8. Green User LED, D2
9. B2B connector Samtec B2B connector Samtec Razor Beam, JM1
10. Programmable clock generator, U10
11. USB2.0 Transceiver,  U18
12. B2B connector Samtec Razor Beam, JM3
13. B2B connector Samtec Razor Beam, JM2
14. 8 GByte eMMC memory, U6
15. Lattice Semiconductor MachXO2 System Controller CPLD, U21

Additional assembly options are available for cost or performance optimization upon request.

Initial Delivery State

...

Configuration Signals

...

*changable also with other CPLD Firmware: TE0821 CPLD.

...

For detailed information about the pin-out, please refer to the Pin-out table.

JTAG Interface

JTAG access to the Xilinx Zynq UltraScale+ is applicable by using Lattice MachXO CPLD  through B2B connector JM2.

...

There are 4x MGT Lanes connected to FPGA Bank 505-GTR. The Xilinx Zynq UltraScale+ device used on the TE0821 module has 4 GTR transceivers. All 4 are wired directly to B2B connector JM3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Gigabit Ethernet

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 chip. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U11), the 125MHz output clock is left unconnected.

MIO Pins

System Controller CPLD

Special purpose pins are connected to System Controller CPLD and have following default configuration:

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

Test Points

...

you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Please check the entire information at TE0821 CPLD.

USB Interface

USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V. Reference clock input for the USB PHY is supplied by the on-board 52.00 MHz oscillator (U14). 

I2C Interface

On-board I²C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I²C0 by default. Addresses for on-board I²C slave devices are listed in the table below:

MIO Pins

...

...

Page properties
hidden true id Comments
Notes : add subsection for every component which is important for design, for example: Two 100 Mbit Ethernet Transciever PHY USB PHY Programmable Clock Generator Oscillators eMMCs RTC FTDI ... DIP-Switches Buttons LEDs
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin Connected to B2B Notes MIO12...14 SPI_CS , SPI_DQ0... SPI_DQ3, SPI_SCK J2 QSPI
Page properties
hidden true id Comments
Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

Designator

Scroll Title
anchor Table_OBPSIP_MIOs title On board peripheralsMIOs pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true MIO Pin Connected to B2B	Chip/Interface

	Notes
0...5	QSPI Flash

, U7

, U17EEPROM

-

U25DDR4 SDRAMU2,U3OscillatorsU32, U14, U11CPLDU21LEDsD1...3