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Table of Contents

Table of Contents

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The Trenz Electronic TE0821 -01-3BI21FA is a powerful 4 x 5 cm MPSoC module integrated with a Xilinx Zynq UltraScale+ MPSoC. In addition, the module is equipped with a 2 2x 1 GB DDR4 SDRAM chip, 4Gb up to 128 Gb eMMC chip,  2x 64 MB flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages.  The module is equipped with a Lattice Mach XO2 CPLD for system controlling. 3x Robust high-speed connectors provide a large number of inputs and outputs.

This module is pin compatible with Trenz Electronic TE0820 MPSoC modules (JM2 pin 100 is not connected).

The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.

All components cover at least the industrial temperature range from -40 ° C to + 85 ° C. The temperature range in which the module can be used depends on the customer design and the selected cooling. Please contact us for special solutions.

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  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2EG, ZU3EG, ZU4EG, ZU5EGZU2 ...ZU5, *
    • Engine:  G (General Purpose) EG, CG, EV, *
    • Speed: -1 (slowest), -1L, -2, -2L, 3, *, **
    • Temperature: I, E, *, **Temperature: Industrial (-40 ~ 85 °C)
  • RAM/Storage
    • 2 GByte 2x  DDR4 SDRAM, 32-Bit databus-width
      • Data Width: 16 Bit
      • Size: 8 Gb, *
      • Speed: 2400 Mbps, ***
    • 2x 128 MByte QSPI boot Flash in dual parallel mode
      • Data Width: 8 Bit
      • Size: 512 Mb Gb, *
    • 1x e.MMC Memory
      • Data Width: 16 Bit
      • Size: 8 Gb, *
      8 GByte e.MMC Memory (up to 64 GByte)
    • MAC address serial EEPROM with EUI-48 node identity
  • On Board
    • Graphic Processing Unit (GPU) :Mali-400 MP2
    • Lattice MachXO2 CPLD
    • Programmable Clock Generator
    • Hi-speed USB2 ULPI Transceiver
    • 4x LEDS
  • Interface
    • 1 Gbps RGMII Ethernet
    Interface
    • PCI Express interface version 2.1 compliant
    • SATA 3.1 specification compliant interface

    • DisplayPort source-only interface with video resolution up to 4k x 2k

    • USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
    • 1 GB/s serial GMII interface
    • Hi-speed USB2 ULPI transceiver with full OTG support
    • Graphic Processor Mali-400 MP2, *
    • 156 x High Performance (HP) und 34 x High Performance und 96 x High Density PL I/Os14
    • 4 x PS MIOs (6 of the MIOs intended for SD card interface in default configuration)
    • 4 x serial PS GTR transceivers
    • serial PS GTR transceivers
      • PCI Express interface
      • SATA 3.1 interface

      • DisplayPort interface with video resolution up to 4k x 2k

      • 2x USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
      Rugged for shock and high vibration
  • Power
    • All power supplies regulators on board
  • Dimension
    • 40 x 50 mm
  • Note
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination
    • Rugged for shock and high vibration

Block Diagram

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Scroll Title
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titleTE0821 block diagram


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Main Components

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titleTE0821 main components


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  1. Xilinx Zynq ZYNQ UltraScale+ XCZU3EGMPSoC, U1
  2. Red LED (ERR_OUT), D3
  3. Green LED (ERR_STATUS), D4
  4. Red LED (DONE), D1
  5. 10/100/1000 Mbps energy efficient ethernet transceiverEnergy Efficient Ethernet Transceiver, U8
  6. 8Gb DDR4, U2-U3
  7. 512 Mbit QSPI flash memory, U7-U17
  8. Green User LED, D2
  9. B2B connector Samtec Razor Beam, JM1
  10. Green User LED, D2
  11. Programmable clock generator, U10
  12. USB2.0 Transceiver,  U18
  13. B2B connector Samtec Razor Beam, JM3
  14. B2B connector Samtec Razor Beam, JM2
  15. 8 GByte eMMC memory, U6
  16. Lattice Semiconductor MachXO2 System Controller CPLD, U21

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titleInitial delivery state of programmable devices on the module

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Storage device name

Content

Notes

Dual QSPI Flash Memory

Not programmed


eMMC Memory

Not programmed


DDR4 SDRAMNot programmed
Programmable Clock GeneratorNot programmed
CPLD (LCMXO2-256HC)???? FirmwareProgrammedTE0821 CPLD


Configuration Signals

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titleBoot process.

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MODE Pin

Boot Mode
LowHigh

QSPI*

HighLowSD Card*


*changable also with other CPLD Firmware: TE0821 CPLD.


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titleReset process.

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Signal

B2BI/ONote

EN

JM1-28InputCPLD Enable Pin

Please refer to the TE0821 CPLD-Bootmode.



Signals, Interfaces and Pins

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titleGeneral PL I/O to B2B connectors information

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FPGA BankTypeB2B ConnectorI/O Signal CountVoltage LevelNotes
24HDJM224x I/O, 12x  LVDS PairsVariable Max voltage 3.3V
25HDJM1

24x I/O, 12x  LVDS Pairs

Variable Max voltage 3.3V
26HDJM124x I/O, 12x  LVDS PairsVariable Max voltage 3.3V
44HDJM224x I/O, 12x  LVDS PairsVariableMax voltage 3.3V
65

HP

JM2

18x I/O, 9x LVDS Pairs

VariableMax voltage 1.8V

65

HP

JM3

16x I/O, 8x LVDS Pairs

Variable

Max voltage 1.8V
505GTRJM316x I/O, 8x LVDS Pairs-4x lanes
505GTR CLKJM31x Diff Clock-

501

MIO

JM1

15 I/O

3.3V



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titleTest Points Information

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Test PointSignalConnected toNotes
1I2C_SCLEEPROM, U25
2I2C_SDAEEPROM, U25
3SRST_BFPGA Bank 503PSCONFIG
4PS_CLKFPGA Bank 503PSCONFIG
5PROG_BFPGA Bank 503PSCONFIG
6INIT_BFPGA Bank 503PSCONFIG
7DONERed LED, D1
8PS_LP0V85Voltage Regulator, U12
9DDR_2V5Voltage Regulator, U4
10PS_AVCCVoltage Regulator, U9
11DDR_1V2Voltage Regulator, U15
12PS_AVTTVoltage Regulator, U3U13
13PS_FP0V85Voltage Regulator, U26
14POR_BVoltage Translator, U19
15PS_PLLVoltage Regulator, U23
16PL_VCCINTVoltage Regulator, U5


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titleOn board peripherals

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Chip/InterfaceDesignatorNotes
QSPI FlashU7, U17
EEPROMU25
DDR4 SDRAMU2,U3
GigaBit EthernetU8
USB2.0 TransceiverU18
eMMC MemoryU6
OscillatorsU32, U14, U11
Programmable Clock GeneratorU25U10
CPLDU21
LEDsD1...3


Quad SPI Flash Memory

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titleProgrammable Clock Generator Inputs and Outputs

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U25 PinSignalConnected toDirectionNote

IN0..1

CLK_INJM3IN
IN2CLK_25MOscillator, U11IN
SCLI2C_SCLEEPROM,U25INOUT
SDAI2C_SDAEEPROM,U25INOUT
CLK0CLK0JM3OUT
CLK1B505_CLK3FPGA Bank 505IN
CLK2B505_CLK1FPGA Bank 505IN
CLK3CLK3_N
IN


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titlePower DistributionDistribution


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titlePower Sequency


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Power Rails

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titleModule power rails.

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Power Rail Name

B2B JM1 Pin

B2B JM2 Pin

B2B JM3 Pin

Direction

Notes
VIN

1, 3, 5

2, 4, 6, 8-InputSupply voltage from the carrier board
3.3V-10, 12-OutputInternal 3.3V voltage level
VCCO_HD25_269,11
-Input0 to 3.3V Voltage
3.3VIN13, 15--InputSupply voltage from the carrier board
1.8V39--OutputInternal 1.8V voltage level
JTAG VREF-91-OutputJTAG reference voltage.
Attention: Net name on schematic is "3.3VIN"
VCCO_HD24_
64
44-7, 9-Input
High performance I/O bank voltage
0 to 3.3V Voltage
VCCO_65-5-Input
High performance I/O bank voltage
0 to 1.8V Voltage
PSBATT79-
VCCO_669, 11
-Input
High performance I/O bank voltage
1.2 to 1.5V Voltage


Bank Voltages

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titleZynq SoC bank voltages.

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FPGA BankSchematicVoltageNote
Bank 24 HDVCCO_HD24_2444Variable Max voltage 3.3V
Bank 25 HDVCCO_HD25_26Variable Max voltage 3.3V
Bank 26 HDVCCO_HD25_26Variable Max voltage 3.3V
Bank 44 HDVCCO_HD24_44VariableMax voltage 3.3V
Bank 64 HPVCCO_64N.CNot Connected
Bank 65 HP

VCCO_65

VariableMax voltage 1.8V
Bank 66 HPVCCO_661.8V
Bank 500 PSMIOVCCO_PSIO0_5001.8V

Bank 501 PSMIO

VCCO_PSIO1_501

3.3V


Bank 502 PSMIOVCCO_PSIO2_5021.8V
Bank 503 PSCONFIGVCCO_PSIO3_5031.8V
Bank 504 PSDDRDDR_1V21.2V



Board to Board Connectors

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  • This section is optional and only for modules.

  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

    Include Page
    PD:6 x 6 SoM LSHM B2B ConnectorsPD:
    6 x 6 SoM LSHM B2B Connectors

Include Page
PD:4 x 5 SoM LSHM B2B ConnectorsPD:
4 x 5 SoM LSHM B2B Connectors

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titlePS absolute maximum ratings

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13.630 DS925 and TPS27082L datasheetPS _PSIO3630PS 5_PSIO 20HP
DescriptionMinMaxUnitNotes

VIN supply voltage

-0.3

7

V

See EN6347QI and TPS82085SIL datasheets3.3VIN supply
3.3VIN supply voltage-0.13.630VXilinx DS925 and TPS27082L datasheet
PS I/O supply voltage, VCCO_PSIO-0.53.630VXilinx document DS925
PS I/O input voltage-0.5VCCO_PSIO + 0.55VXilinx document DS925
HP I/O bank supply voltage, VCCO-0.52.0VXilinx document DS925
HP I/O bank input voltage-0.55VCCO + 0.55VXilinx document DS925HP
HD I/O bank supply voltage, VCCO-0.53.4VXilinx document DS925
HD I/O bank input voltage-0.55VCCO + 0.55VXilinx document DS925
PS GTR reference clocks absolute input voltage-0.51.1VXilinx document DS925
PS GTR absolute input voltage-0.51.1VXilinx document DS925

Voltage on SC CPLD pins

-0.5

3.75

V

Lattice Semiconductor MachXO2 datasheet

Storage temperature

-40

+85

°C

See eMMC datasheet


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Scroll Title
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titleRecommended operating conditions.

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095019HP
ParameterMinMaxUnitsReference Document
VIN supply voltage3.36VSee TPS82085S datasheet
3.3VIN supply voltage3.33.465VSee LCMXO2-256HC, Xilinx DS925 datasheet
PS I/O supply voltage, VCCO_PSIO1.7103.465VXilinx document DS925
PS I/O input voltage–0.20VCCO_PSIO + 0.20VXilinx document DS925
HP I/O banks supply voltage, VCCO_PSIO10.71095031.4659VXilinx document DS925
PS HP I/O banks input voltage–0-0.20VCCO _PSIO + 0.20VXilinx document DS925HP
HD I/O banks supply voltage, VCCO1.143.4VXilinx document DS925
HD I/O banks input voltage-0.20VCCO + 0.20VXilinx document DS925
Voltage on SC CPLD pins-0.33.6VLattice Semiconductor MachXO2 datasheet
Operating Temperature Range085°CXilinx document DS925, extended grade Zynq temperarure range


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titleBoard hardware revision number.


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Document Change History

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DateRevisionContributorDescription

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  • bugfix boot mode

2021-07-05v.61John Hartfiel

  • Update download Link

  • Update Change history
2021-06-07v.59Vadim Yunitski
  • Added missing text in Bank Voltages
  • Fixed typo in Bank Voltages
2020-07-15v.50Pedram Babakhani
  • Initial Release

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