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The Trenz Electronic TE0821 is a powerful 4 x 5 cm MPSoC module integrated with a Xilinx Zynq UltraScale+ MPSoC. In addition, the module is equipped with a 2 2x 1 GB DDR4 SDRAM chip, 4Gb up to 128 Gb eMMC chip,  2x 64 MB flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages.  The module is equipped with a Lattice Mach XO2 CPLD for system controlling. 3x Robust high-speed connectors provide a large number of inputs and outputs.

This module is pin compatible with Trenz Electronic TE0820 MPSoC modules (JM2 pin 100 is not connected).

The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.

All components cover at least the industrial temperature range from -40 ° C to + 85 ° C. The temperature range in which the module can be used depends on the customer design and the selected cooling. Please contact us for special solutions.

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• SoC/FPGA
  
  • Package: SFVC784
  • Device: ZU2EG, ZU3EG, ZU4EG, ZU5EGZU2 ...ZU5, *
  • Engine:  G (General Purpose) EG, CG, EV, *
  • Speed: -1 (slowest), -1L, -2, -2L, 3, *, **
  • Temperature: I, E, *, **Temperature: Industrial (-40 ~ 85 °C)
• RAM/Storage
  • 2 GByte 2x  DDR4 SDRAM, 32-Bit databus-width
    • Data Width: 16 Bit
    • Size: 8 Gb, *
    • Speed: 2400 Mbps, ***
  • 2x 128 MByte QSPI boot Flash in dual parallel mode
    • Data Width: 8 Bit
    • Size: 512 Mb Gb, *
  • 1x e.MMC Memory
    • Data Width: 16 Bit
    • Size: 8 Gb, *
    8 GByte e.MMC Memory (up to 64 GByte)
  • MAC address serial EEPROM with EUI-48 node identity
• On Board
  
  • Graphic Processing Unit (GPU) :Mali-400 MP2
  
  
  • Lattice MachXO2 CPLD
  • Programmable Clock Generator
  • Hi-speed USB2 ULPI Transceiver
  • 4x LEDS
• Interface
  • 1 Gbps RGMII Ethernet
  Interface
  • PCI Express interface version 2.1 compliant
  • SATA 3.1 specification compliant interface

  • DisplayPort source-only interface with video resolution up to 4k x 2k

  • USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
  • 1 GB/s serial GMII interface
  • Hi-speed USB2 ULPI transceiver with full OTG support
  • Graphic Processor Mali-400 MP2, *
  • 156 x High Performance (HP) und 34 x High Performance und 96 x High Density PL I/Os14 x PS MIOs (6 of the MIOs intended for SD card interface in default configuration)Os
  • 4 x serial PS GTR transceivers
    Rugged for shock and high vibration
    • PCI Express interface
    • SATA 3.1 interface

    • DisplayPort interface with video resolution up to 4k x 2k

    • 2x USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
  • Power
    • All power supplies regulators on board
  • Dimension
    • 40 x 50 mm
  • Note
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination
    • Rugged for shock and high vibration

  Block Diagram

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  Scroll Title
  anchor Figure_OV_BD title TE0821 block diagram
  Scroll Ignore draw.io Diagram border false diagramName TE0821_OV_BD simpleViewer false width links auto tbstyle hidden diagramDisplayName lbox true diagramWidth 641 revision 819 Scroll Only

  Main Components

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  Scroll Title
  anchor Figure_OV_MC title TE0821 main components
  Scroll Ignore draw.io Diagram border false diagramName TE0821_OV_MC simpleViewer false width links auto tbstyle hidden diagramDisplayName lbox true diagramWidth 641 revision 89 Scroll Only

  1. Xilinx Zynq ZYNQ UltraScale+ XCZU3EGMPSoC, U1
  2. Red LED (ERR_OUT), D3
  3. Green LED (ERR_STATUS), D4
  4. Red LED (DONE), D1
  5. 10/100/1000 Mbps energy efficient ethernet transceiverEnergy Efficient Ethernet Transceiver, U8
  6. 8Gb DDR4, U2-U3
  7. 512 Mbit QSPI flash memory, U7-U17
  8. Green User LED, D2
  9. B2B connector Samtec Razor Beam, JM1
  10. Programmable clock generator, U10
  11. USB2.0 Transceiver,  U18
  12. B2B connector Samtec Razor Beam, JM3
  13. B2B connector Samtec Razor Beam, JM2
  14. 8 GByte eMMC memory, U6
  15. Lattice Semiconductor MachXO2 System Controller CPLD, U21

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  Scroll Title
  anchor Table_OV_IDS title Initial delivery state of programmable devices on the module
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Storage device name Content Notes Dual QSPI Flash Memory Not programmed eMMC Memory Not programmed DDR4 SDRAM Not programmed Programmable Clock Generator Not programmed CPLD (LCMXO2-256HC) ???? FirmwareProgrammed TE0821 CPLD

  Configuration Signals

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  Scroll Title
  anchor Table_OV_BP title Boot process.
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true MODE Pin Boot Mode LowHigh QSPI* HighLow SD Card*

  *changable also with other CPLD Firmware: TE0821 CPLD.

  
  

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  anchor Table_OV_RST title Reset process.
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Signal B2B I/O Note EN JM1-28 Input CPLD Enable Pin

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  Signals, Interfaces and Pins

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  anchor Table_SIP_B2B title General PL I/O to B2B connectors information
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true FPGA Bank Type B2B Connector I/O Signal Count Voltage Level Notes 24 HD JM2 24x I/O, 12x  LVDS Pairs Variable  Max voltage 3.3V 25 HD JM1 24x I/O, 12x  LVDS Pairs Variable  Max voltage 3.3V 26 HD JM1 24x I/O, 12x  LVDS Pairs Variable  Max voltage 3.3V 44 HD JM2 24x I/O, 12x  LVDS Pairs Variable Max voltage 3.3V 65 HP JM2 18x I/O, 9x LVDS Pairs Variable Max voltage 1.8V 65 HP JM3 16x I/O, 8x LVDS Pairs Variable Max voltage 1.8V 505 GTR JM3 16x I/O, 8x LVDS Pairs - 4x lanes 505 GTR CLK JM3 1x Diff Clock - 501 MIO JM1 15 I/O 3.3V

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  Scroll Title
  anchor Table_SIP_TPs title Test Points Information
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Test Point Signal Connected to Notes 1 I2C_SCL EEPROM, U25 2 I2C_SDA EEPROM, U25 3 SRST_B FPGA Bank 503 PSCONFIG 4 PS_CLK FPGA Bank 503 PSCONFIG 5 PROG_B FPGA Bank 503 PSCONFIG 6 INIT_B FPGA Bank 503 PSCONFIG 7 DONE Red LED, D1 8 PS_LP0V85 Voltage Regulator, U12 9 DDR_2V5 Voltage Regulator, U4 10 PS_AVCC Voltage Regulator, U9 11 DDR_1V2 Voltage Regulator, U15 12 PS_AVTT Voltage Regulator, U3U13 13 PS_FP0V85 Voltage Regulator, U26 14 POR_B Voltage Translator, U19 15 PS_PLL Voltage Regulator, U23 16 PL_VCCINT Voltage Regulator, U5

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  Power Distribution Dependencies

  title

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  anchor Figure_PWR_PD title Power Distribution
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  Scroll Title
  anchor Table_PWR_PR title Module power rails.
  Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Power Rail Name B2B JM1 Pin B2B JM2 Pin B2B JM3 Pin Direction Notes VIN 1, 3, 5 2, 4, 6, 8 - Input Supply voltage from the carrier board 3.3V - 10, 12 - Output Internal 3.3V voltage level VCCO_HD25_26 9,11 - Input 0 to 3.3V Voltage 3.3VIN 13, 15 - - Input Supply voltage from the carrier board 1.8V 39 - - Output Internal 1.8V voltage level JTAG VREF - 91 - Output JTAG reference voltage. Attention: Net name on schematic is "3.3VIN" VCCO_HD24_ 64 44 - 7, 9 - Input High performance I/O bank voltage 0 to 3.3V Voltage VCCO_65 - 5 - Input	High performance I/O bank voltage

  	0 to 1.8V Voltage
  PSBATT	79	-

  VCCO_669, 11

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  Input

  High performance I/O bank voltage

  1.2 to 1.5V Voltage