...
Page properties |
---|
|
Note for Download Link of the Scroll ignore macro: |
Scroll pdf ignore |
---|
Table of Contents |
...
- SoC/FPGA
- Package: SFVC784
- Device: ZU2 ...ZU5, *
- Engine: EG, CG, EV, *
- Speed: -1, -1L, -2, -2L, 3, *, **
- Temperature: I, E, *, **
- RAM/Storage
- 2x DDR4 SDRAM,
- Data Width: 16 Bit
- Size: 8 Gb, *
- Speed: 2400 Mbps, ***
- 2x QSPI boot Flash in dual parallel mode
- Data Width: 8 Bit
- Size: 512 Mb Gb, *
- 1x e.MMC Memory
- Data Width: 16 Bit
- Size: 8 Gb, *
- MAC address serial EEPROM
- On Board
- Lattice MachXO2 CPLD
- Programmable Clock Generator
- Hi-speed USB2 ULPI Transceiver
- 4x LEDS
- Interface
- 1 GB/s serial GMII Gbps RGMII Ethernet interface
- Hi-speed USB2 ULPI transceiver with full OTG support
- Graphic Processor Mali-400 MP2, *
- 156 34 x High Performance (HP) und 96 x High Density PL I/Os14 x PS MIOs (6 of the MIOs intended for SD card interface in default configuration)
- 4 x serial PS GTR transceivers
- Power
- All power regulators on board
- Dimension
- Note
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
- Rugged for shock and high vibration
...
Scroll Title |
---|
anchor | Figure_OV_BD |
---|
title | TE0821 block diagram |
---|
|
Scroll Ignore |
---|
draw.io Diagram |
---|
border | false |
---|
| |
---|
diagramName | TE0821_OV_BD |
---|
simpleViewer | false |
---|
width | |
---|
links | auto |
---|
tbstyle | hidden |
---|
diagramDisplayName | |
---|
lbox | true |
---|
diagramWidth | 641 |
---|
revision | 919 |
---|
|
|
Scroll Only |
---|
|
|
Main Components
...
Scroll Title |
---|
anchor | Figure_OV_MC |
---|
title | TE0821 main components |
---|
|
Scroll Ignore |
---|
draw.io Diagram |
---|
border | false |
---|
| |
---|
diagramName | TE0821_OV_MC |
---|
simpleViewer | false |
---|
width | |
---|
links | auto |
---|
tbstyle | hidden |
---|
diagramDisplayName | |
---|
lbox | true |
---|
diagramWidth | 641 |
---|
revision | 9 |
---|
|
|
Scroll Only |
---|
|
|
- Xilinx Zynq ZYNQ UltraScale+ XCZU3EGMPSoC, U1
- Red LED (ERR_OUT), D3
- Green LED (ERR_STATUS), D4
- Red LED (DONE), D1
- 10/100/1000 Mbps energy efficient ethernet transceiverEnergy Efficient Ethernet Transceiver, U8
- 8Gb DDR4, U2-U3
- 512 Mbit QSPI flash memory, U7-U17
- Green User LED, D2
- B2B connector Samtec Razor Beam, JM1
- Programmable clock generator, U10
- USB2.0 Transceiver, U18
- B2B connector Samtec Razor Beam, JM3
- B2B connector Samtec Razor Beam, JM2
- 8 GByte eMMC memory, U6
- Lattice Semiconductor MachXO2 System Controller CPLD, U21
...
Scroll Title |
---|
anchor | Table_OV_IDS |
---|
title | Initial delivery state of programmable devices on the module |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Storage device name | Content | Notes |
---|
Dual QSPI Flash Memory | Not programmed |
| eMMC Memory | Not programmed |
| DDR4 SDRAM | Not programmed |
| Programmable Clock Generator | Not programmed |
| CPLD (LCMXO2-256HC) | Programmed | TE0821 CPLD |
|
...
Scroll Title |
---|
anchor | Table_OV_BP |
---|
title | Boot process. |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
MODE Pin | Boot Mode |
---|
LowHigh | QSPI* | HighLow | SD Card* |
|
*changable also with other CPLD Firmware: Please refer to the TE0821 CPLD.
Scroll Title |
---|
anchor | Table_OV_RST |
---|
title | Reset process. |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Signal | B2B | I/O | Note |
---|
EN | JM1-28 | Input | CPLD Enable Pin |
|
...
Scroll Title |
---|
anchor | Table_SIP_B2B |
---|
title | General PL I/O to B2B connectors information |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
FPGA Bank | Type | B2B Connector | I/O Signal Count | Voltage Level | Notes |
---|
24 | HD | JM2 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 25 | HD | JM1 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 26 | HD | JM1 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 44 | HD | JM2 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 65 | HP | JM2 | 18x I/O, 9x LVDS Pairs | Variable | Max voltage 1.8V | 65 | HP | JM3 | 16x I/O, 8x LVDS Pairs | Variable | Max voltage 1.8V | 505 | GTR | JM3 | 16x I/O, 8x LVDS Pairs | - | 4x lanes | 505 | GTR CLK | JM3 | 1x Diff Clock | - |
| 501 | MIO | JM1 | 15 I/O | 3.3V |
|
|
...
Scroll Title |
---|
anchor | Table_SIP_TPs |
---|
title | Test Points Information |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Test Point | Signal | Connected to | Notes |
---|
1 | I2C_SCL | EEPROM, U25 |
| 2 | I2C_SDA | EEPROM, U25 |
| 3 | SRST_B | FPGA Bank 503 | PSCONFIG | 4 | PS_CLK | FPGA Bank 503 | PSCONFIG | 5 | PROG_B | FPGA Bank 503 | PSCONFIG | 6 | INIT_B | FPGA Bank 503 | PSCONFIG | 7 | DONE | Red LED, D1 |
| 8 | PS_LP0V85 | Voltage Regulator, U12 |
| 9 | DDR_2V5 | Voltage Regulator, U4 |
| 10 | PS_AVCC | Voltage Regulator, U9 |
| 11 | DDR_1V2 | Voltage Regulator, U15 |
| 12 | PS_AVTT | Voltage Regulator, U3U13 |
| 13 | PS_FP0V85 | Voltage Regulator, U26 |
| 14 | POR_B | Voltage Translator, U19 |
| 15 | PS_PLL | Voltage Regulator, U23 |
| 16 | PL_VCCINT | Voltage Regulator, U5 |
|
|
...
Scroll Title |
---|
anchor | Table_OBP |
---|
title | On board peripherals |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
|
Quad SPI Flash Memory
...
Scroll Title |
---|
anchor | Table_PWR_BV |
---|
title | Zynq SoC bank voltages. |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
FPGA Bank | Schematic | Voltage | Note |
---|
Bank 24 HD | VCCO_HD24_2444 | Variable | Max voltage 3.3V | Bank 25 HD | VCCO_HD25_26 | Variable | Max voltage 3.3V | Bank 26 HD | VCCO_HD25_26 | Variable | Max voltage 3.3V | Bank 44 HD | VCCO_HD24_44 | Variable | Max voltage 3.3V | Bank 64 HP | VCCO_64 | N.C | Not Connected | Bank 65 HP | VCCO_65 | Variable | Max voltage 1.8V | Bank 66 HP | VCCO_66 | 1.8V |
| Bank 500 PSMIO | VCCO_PSIO0_500 | 1.8V |
| Bank 501 PSMIO | VCCO_PSIO1_501 | 3.3V |
| Bank 502 PSMIO | VCCO_PSIO2_502 | 1.8V |
| Bank 503 PSCONFIG | VCCO_PSIO3_503 | 1.8V |
| Bank 504 PSDDR | DDR_1V2 | 1.2V |
|
|
...
Page properties |
---|
|
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
---|
| PD:6 x 6 SoM LSHM B2B ConnectorsPD: |
---|
| 6 x 6 SoM LSHM B2B Connectors |
---|
|
|
Include Page |
---|
| PD:4 x 5 SoM LSHM B2B ConnectorsPD: |
---|
| 4 x 5 SoM LSHM B2B Connectors |
---|
|
...
Scroll Title |
---|
anchor | Table_TS_AMR |
---|
title | PS absolute maximum ratings |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Description | Min | Max | Unit | Notes |
---|
VIN supply voltage | -0.3 | 7 | V | See EN6347QI and TPS82085SIL datasheets | 3.3VIN supply voltage | -0.1 | 3.630 | V | Xilinx DS925 and TPS27082L datasheet | PS I/O supply voltage, VCCO_PSIO | -0.5 | 3.630 | V | Xilinx document DS925 | PS I/O input voltage | -0.5 | VCCO_PSIO + 0.55 | V | Xilinx document DS925 | HP I/O bank supply voltage, VCCO | -0.5 | 2.0 | V | Xilinx document DS925 | HP I/O bank input voltage | -0.55 | VCCO + 0.55 | V | Xilinx document DS925 | HD I/O bank supply voltage, VCCO | -0.5 | 3.4 | V | Xilinx document DS925 | HD I/O bank input voltage | -0.55 | VCCO + 0.55 | V | Xilinx document DS925 | PS GTR reference clocks absolute input voltage | -0.5 | 1.1 | V | Xilinx document DS925 | PS GTR absolute input voltage | -0.5 | 1.1 | V | Xilinx document DS925 | Voltage on SC CPLD pins | -0.5 | 3.75 | V | Lattice Semiconductor MachXO2 datasheet | Storage temperature | -40 | +85 | °C | See eMMC datasheet |
|
...
Scroll Title |
---|
anchor | Figure_RV_HRN |
---|
title | Board hardware revision number. |
---|
|
Scroll Ignore |
---|
draw.io Diagram |
---|
border | false |
---|
| |
---|
diagramName | TE0821_RV_HRN |
---|
simpleViewer | false |
---|
width | |
---|
links | auto |
---|
tbstyle | hidden |
---|
diagramDisplayName | |
---|
lbox | true |
---|
diagramWidth | 326 |
---|
revision | 34 |
---|
|
|
Scroll Only |
---|
|
|
Document Change History
...
Scroll Title |
---|
anchor | Table_RH_DCH |
---|
title | Document change history. |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Date | Revision | Contributor | Description |
---|
Page info |
---|
infoType | Modified date |
---|
dateFormat | yyyy-MM-dd |
---|
type | Flat |
---|
|
| Page info |
---|
infoType | Current version |
---|
prefix | v. |
---|
type | Flat |
---|
showVersions | false |
---|
|
| Page info |
---|
infoType | Modified by |
---|
type | Flat |
---|
showVersions | false |
---|
|
| | 2021-07-05 | v.61 | John Hartfiel | Update download Link - Update Change history
| 2021-06-07 | v.59 | Vadim Yunitski | | 2020-07-15 | v.50 | Pedram Babakhani | | -- | all | Page info |
---|
infoType | Modified users |
---|
type | Flat |
---|
showVersions | false |
---|
|
| |
|
...