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The Trenz Electronic TE0022-01 board is an industrial-grade a SoC module based on Intel Cyclone V FPGA, an ethernet PHY, one GByte DDR3 SDRAM and one 32 MByte Quad SPI Flash memory for configuration and operation per HPS and FPGA, and powerful switching-mode power supplies for all on-board voltages.
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- SoC FPGA
- Intel Cyclone V (5CSEMA5F31C8N)
- Package: FBGA 896 pins
- Speed Grade: 8
- Temperature: Commercial (Tj = 0 °C to 85 °C)
- RAM/Storage
- 1 GByte DDR3 SDRAM for HPS
- 1 GByte DDR3 SDRAM for FPGA
- 32 MByte SPI for HPS
- 32 MByte SPI for FPGA
- On Board
- 4 7 x SMA Connector
- Temperature Sensor
- Intel MAX10 for board management
- Interface
- LPC FMC Connector
- 4 x PMOD Connector
- JTAG via micro USB B Connector
- UART via micro USB B Connector
- 4 x USB 2.0
- Ethernet via RJ45 Connector
- SD Card
- HDMI
- Power
- 12 V Input supply voltage
- Dimension
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| Scroll Title |
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Storage device name | Content | Notes |
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HPS SPI Flash (U6) | Not programmed | HPS Configuration | | FPGA SPI Flash (U15) | Not programmed | FPGA Configuration | | MAC EEPROM (U38) | Not Programmed | Ethernet MAC | | System ControllerFTDI EEPROM (U31) | Programmed | Board Management | FTDI EEPROMFunctionality | Programmed |
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Configuration Signals
| Page properties |
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- Overview of Boot Mode, Reset, Enables.
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| Scroll Title |
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| anchor | Table_OV_BP |
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| title | Boot process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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BOOTSEL[1..0] Signal State | DIP-switch S7 position | Boot Mode |
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00 | S7A - ON; S7B - ON | FPGA | | 01 | S7A - ON; S7B - OFF | SD | | 11 | S7A - OFF; S7B - OFF | SPI |
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| Scroll Title |
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| anchor | Table_OV_RST |
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| title | Reset process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Reset | Button | Note |
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HPS cold reset | S1 |
| | HPS warm reset | S3 |
| | FPGA reset | S4 |
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Following table gives an overview of the Pmod connectors and the signals routed to the attached Intel Cyclone V (U10):
| Scroll Title |
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| anchor | Table_SIP_PMOD |
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| title | Pmod connectors pin description |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Pmod Connector P1 Pin | Signal Schematic Name | Connected to | Notes |
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| 1 | P0_IO1 | Intel Cyclone V U10, Pin XAD9 |
| | 2 | P0_IO2 | Intel Cyclone V U10, Pin XAD11 |
| | 3 | P0_IO3 | Intel Cyclone V U10, Pin XAD12 |
| | 4 | P0_IO4 | Intel Cyclone V U10, Pin XAC12 |
| | 7 | P0_IO5 | Intel Cyclone V U10, Pin XAC9 |
| | 8 | P0_IO6 | Intel Cyclone V U10, Pin XAD10 |
| | 9 | P0_IO7 | Intel Cyclone V U10, Pin XAA12 |
| | 10 | P0_IO8 | Intel Cyclone V U10, Pin XAB12 |
| | Pmod Connector P2 Pin | Signal Schematic Name | Connected to | Notes | | 1 | P1_IO1 | Intel Cyclone V U10, Pin X |
| | 2 | P1_IO2 | Intel Cyclone V U10, Pin XAF4 |
| | 3 | P1_IO3 | Intel Cyclone V U10, Pin XAF8 |
| | 4 | P1_IO4 | Intel Cyclone V U10, Pin XAD7 |
| | 7 | P1_IO5 | Intel Cyclone V U10, Pin XAG1 |
| | 8 | P1_IO6 | Intel Cyclone V U10, Pin XAF5 |
| | 9 | P1_IO7 | Intel Cyclone V U10, Pin XAE7 |
| | 10 | P1_IO8 | Intel Cyclone V U10, Pin XAE9 |
| | Pmod Connector P3 Pin | Signal Schematic Name | Connected to | Notes | | 1 | P2_IO1 | Intel Cyclone V U10, Pin XAH5 |
| | 2 | P2_IO2 | Intel Cyclone V U10, Pin XAH3 |
| | 3 | P2_IO3 | Intel Cyclone V U10, Pin XAJ2 |
| | 4 | P2_IO4 | Intel Cyclone V U10, Pin XAG3 |
| | 7 | P2_IO5 | Intel Cyclone V U10, Pin XAG5 |
| | 8 | P2_IO6 | Intel Cyclone V U10, Pin XAH4 |
| | 9 | P2_IO7 | Intel Cyclone V U10, Pin XAH2 |
| | 10 | P2_IO8 | Intel Cyclone V U10, Pin XAJ1 |
| | Pmod Connector P4 Pin | Signal Schematic Name | Connected to | Notes | | 1 | P3_IO1 | Intel Cyclone V U10, Pin XAE12 |
| | 2 | P3_IO2 | Intel Cyclone V U10, Pin XAF9 |
| | 3 | P3_IO3 | Intel Cyclone V U10, Pin XAG8 |
| | 4 | P3_IO4 | Intel Cyclone V U10, Pin XAG6 |
| | 7 | P3_IO5 | Intel Cyclone V U10, Pin XAE11 |
| | 8 | P3_IO6 | Intel Cyclone V U10, Pin XAF10 |
| | 9 | P3_IO7 | Intel Cyclone V U10, Pin XAG7 |
| | 10 | P3_IO8 | Intel Cyclone V U10, Pin XAF6 |
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FMC LPC Connector
The FMC (FPGA Mezzanine Card) connector J4 with low pin count (LPC) provides as an ANSI/VITA 57.1 standard a modular interface to the Intel Cyclone V FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.
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| Scroll Title |
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| anchor | Table_SIP_FMC_Interfaces |
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| title | FMC connector pin-outs of available interfaces |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Interface | I/O Signal Count | Pin schematic Names / FMC Pins | Connected to | Notes |
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| JTAG | 5 | FMC_TCK, Pin J4-D29 FMC_TMS, Pin J4-D33 FMC_TDI, Pin J4-D30 FMC_TDO, Pin J4- D31 FMC_TRST#, Pin J4- D34 | Intel MAX10 U41, Bank 3 | VCCIO: +3.3V | | I2C | 2 | FMC_SCL, Pin J4-C30 FMC_SDA, Pin J4-C31 | Intel MAX10 U41, Bank 3 and Intel Cyclone V U10, Bank 7A | I2C-lines pulled-up to +3.3V | | Control Lines | 2 | FMC_PRSNT_M2C#, Pin J4-H2 (pulled-up to +3.3V) FMC_PG_C2M, Pin J4-D1 (pulled-up to +3.3V) | Intel MAX10 U41, Bank 3 and Intel Cyclone V U10, Bank 5B | 'PG' = 'Power Good'-signal 'C2M' = carrier to (Mezzanine) module 'M2C' = (Mezzanine) module to carrier |
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According to the JTAGEN and JTAGSEL[1..0] pins the management Intel MAX10 (U41), the Intel Cyclone V HPS (U10), the Intel Cyclone V FPGA (U10) or the FMC (J4) can be accessed via the micro USB B connector J13.
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SMA Connector
The TEI0022 board offers four seven SMA connector connectors for trigger and clock input and output connected to the Intel Cyclone V.
| Scroll Title |
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| anchor | Table_SIP_SMA |
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| title | SMA connectors |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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SMA Connector | Signal Schematic Names | Connected to | Notes |
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| J7 | EXT_CLK_INPUT | SMA_CLK_OUT_p | Clock Generator U3, Pin 22 |
| | J10 | SMA_CLK_OUT_n | Clock Generator U3, Pin 21 |
| | J8 | TRIGGER_OUTPUT | Intel Cyclone V U10, Pin | AA26AE29 | J8
| | J9 | CLKTRIGGER_INPUT | Intel Cyclone V U10, Pin | AB27AA26 | J9
| J15 | TRIGGEREXT_CLK_INPUT | Intel Cyclone V U10, Pin | AE29Y26 |
| J10| J17 | TRIGGERCLK_ | OUTPUTINPUT | Intel Cyclone V U10, Pin | AD29AA26 |
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SD Card Connector
| | J18 | SMA_CLK_IN | Clock Generator U3, Pin 1 |
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SD Card Connector
SD Card SD Card connector J3 is connected to the Intel Cyclone V.
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Chip/Interface | Designator | Notes |
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| Temperature Sensor | U16 |
| | QSPI | U6, U15 |
| | EEPROM | U31, U38 |
| | On-Board LEDs | D1...15, D17...23, D25 |
| | DDR3 SDRAM | U26...29 |
| | Gigabit Ethernet PHY | U1 |
| | Clock Sources |
U...| U48, U32, U34 |
| | DIP-Switches | S2, S7...8 |
| | Programmable Clock Generator | U3 |
| | JTAG | U21 |
| | UART | U30 |
| | HDMI | U23 |
| | System Controller Intel MAX10 | U41 |
| | PMOD | P1...4 |
| | Power Monitoring | U54 |
| | High-Speed USB ULPI PHY | U8 |
| | 4-Port USB 2.0 Hub | U33 |
| | SD Card | J3 |
| | Intel Cyclone V | U10 |
| | Buttons | S1, S3...5 |
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Temperatur Sensor
The temperature sensor ADT7410 (U16) is implemented on the TEI0022 board.
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Two 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron MT25QL256ABA8E12, U6, U15) are provided for FPGA and HPS configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA and or the HPS allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.
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| Scroll Title |
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| anchor | Table_OBP_PLL |
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| title | Programmable quad PLL clock generator inputs and outputs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Si5338A Pin | Signal Name / Description | Connected to | Direction | Notes |
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IN1 | - | SMA_CLK_IN | SMA J18, Pin 1Not Connected | Input | Not used |
| | IN2 | - | SMA_CLK_IN | SMA J18, Pin 2GND | Input | Not used |
| IN3 | Reference input clock | U48, Pin 3 | Input | 25 .000000 MHz oscillator U48, SiT8208 | IN4 | - | GND | Input | I2C slave device address LSB | IN5 | - | Not Connected | Input | Not used | | IN6 | - | GND | Input | Not used | | SCL | HPS_I2C_SCL | HPS I2C Bus U10, Pin H23 | Input | I²C interface muxed to FPGAIntel Cyclone V Slave address: 0x70. | | SDA | HPS_I2C_SDA | HPS I2C Bus U10, Pin A25 | Input / Output | I²C interface muxed to FPGAIntel Cyclone V Slave address: 0x70. | CLK0A/B | SMA_CLK_B3BOUT_p/n | U10, Pin AF14/15SMA J7/J10 | Output | Clock to FPGA bank 3BSMA connectors | CLK1A/B | CLK_B4AB3B_p/n | U10, Pin AA16AF14/AB17Output15 |
| Clock to FPGA bank 4A3B | | CLK2A | CLK_50MHz_MAX10 | U41, Pin H6 | Output | Clock to Intel MAX10 bank 2 | | CLK2B | HPS_CLK2_25MHz | U10, Pin F25 | Output | Clock to HPS bank 7A | | CLK3A/B | CLK_ B5BB4A_p/n | U10, Pin Y26AA16/27AB17 | Output | Clock to HPS FPGA bank 5B4A |
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Oscillators
The FPGA module has following reference clocking source provided by an on-board oscillator:
| Scroll Title |
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| anchor | Table_OBP_OSC |
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| title | Reference clock signals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Clock Source | Frequency | Signal Schematic Name | Clock Destination | Notes |
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U48, SiT8208AI
| 25.0 MHz
| CLK_25MHz_R
| Si5338A PLL U3, Pin 3 (IN3) |
| | HPS_CLK1_25MHz | HPS Bank 7A U10, Pin D25 |
| | ETH_XTAL_IN | ETH PHY U1, Pin 9 |
| | U32, SiT8208AI | 12.0 MHz | OSCI | FT2232H U21, Pin 3 |
| | U34, SiT8008BI | 24.0 MHz | USB_CLK24_HUB | USB Hub U33, Pin 33 |
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| USB_CLK24_PHY | USB PHY U8, Pin 26 |
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I2C
The TEI0022 provides two three independent I2C busses. One bus is used to connect the FMC I2C with the Intel Cyclone V HPS. The second bus is to connect the HDMI device to the Intel Cyclone V FPGA. The other third bus is used to handle the other on-board I2C devices.
| Scroll Title |
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| anchor | Table_OBP_I2C |
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| title | On-board peripherals' I2C-interfaces device slave addresses |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Bus | I2C Device | Designator | I2C Address | Schematic Names of I2C Bus Lines | Notes |
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| HPS I2C | Temperature Sensor | 0x4A | U16 | HPS_I2C_SCL / HPS_I2C_SDA | 3.3 V reference voltage | | HPS I2C | Programmable Clock Generator | 0x70 | U3 | HPS_I2C_SCL / HPS_I2C_SDA | 3.3 V reference voltage | | HPS I2C | EEPROM | 0x50 | U38 | HPS_I2C_SCL / HPS_I2C_SDA | 3.3 V reference voltage | | HPS HDMI I2C | HDMI | 0x72 | U23 | HPS_I2C_SCL / HPS_I2C_SDA | 3.3 V reference voltage | | HPS FMC I2C | FMC | 0x50 | J4 | FMC_SCL / FMC_SDA | 3.3 V reference voltage |
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