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Pmod Connector
The TEI0022 board offers four Pmod (2x6 pins, SMD) connectors which provides as a standard modular interface single ended I/O pins for use with extension modules.
JTAG Interface
Following table gives an overview of the Pmod connectors and the signals routed to the attached Intel Cyclone V (U10):According to the JTAGEN and JTAGSEL[1..0] pins the management Intel MAX10 (U41), the Intel Cyclone V HPS (U10), the Intel Cyclone V FPGA (U10) or the FMC (J4) can be accessed via the micro USB B connector J13.
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I2C
The TEI0022 provides three independent I2C busses. One bus is used to connect the FMC I2C with the Intel Cyclone V HPS. The second bus is to connect the HDMI device to the Intel Cyclone V FPGA. The third bus is used to handle the other on-board I2C devices.
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Pmod Connector
The TEI0022 board offers four Pmod (2x6 pins, SMD) connectors which provides as a standard modular interface single ended I/O pins for use with extension modules.
Following table gives an overview of the Pmod connectors and the signals routed to the attached Intel Cyclone V (U10):
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FMC LPC Connector
The FMC (FPGA Mezzanine Card) connector J4 with low pin count (LPC) provides as an ANSI/VITA 57.1 standard a modular interface to the Intel Cyclone V FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.
The connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.
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The FMC connector provides further interfaces like JTAG and I²C interfaces:
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FMC_TCK, Pin J4-D29
FMC_TMS, Pin J4-D33
FMC_TDI, Pin J4-D30
FMC_TDO, Pin J4- D31
FMC_TRST#, Pin J4- D34
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FMC_SCL, Pin J4-C30
FMC_SDA, Pin J4-C31
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FMC_PRSNT_M2C#, Pin J4-H2 (pulled-up to +3.3V)
FMC_PG_C2M, Pin J4-D1 (pulled-up to +3.3V)
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'PG' = 'Power Good'-signal
'C2M' = carrier to (Mezzanine) module
'M2C' = (Mezzanine) module to carrier
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FMC LPC Connector
The FMC (FPGA Mezzanine Card) connector J4 with low pin count (LPC) provides as an ANSI/VITA 57.1 standard a modular interface to the Intel Cyclone V FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.
The connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.Several VCCIO voltages are available on the FMC connector to operate the I/O's on different voltage levels:
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| +12.0V_FMC | C35/C37 | extern 12V power supply | ||||||||||||||||
| +3.3V_FMC | D36/D38/D40/C39 | 3.3V peripheral supply voltage | ||||||||||||||||
| +3.3V | D32 | 3.3V peripheral supply voltage | ||||||||||||||||
| FMC_VADJ | H40/G39 | adjustable FMC VCCIO voltage, supplied by DC-DC converter U43 | ||||||||||||||||
| FMC_VREF_A_M2C | H1 | adjustable reference voltage |
JTAG Interface
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The FMC connector provides further interfaces like JTAG and I²C interfaces:According to the JTAGEN and JTAGSEL[1..0] pins the management Intel MAX10 (U41), the Intel Cyclone V HPS (U10), the Intel Cyclone V FPGA (U10) or the FMC (J4) can be accessed via the micro USB B connector J13.
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JTAGSEL1 | JTAGSEL0 | JTAGSEL1 | JTAGSEL0 | |||||||||||||||
| X | X | ON | Intel MAX10 | |||||||||||||||
| ON | ON | OFF | Intel Cyclone V HPS | |||||||||||||||
| ON | OFF | OFF | Intel Cyclone V FPGA | |||||||||||||||
| OFF | ON | OFF | FMC |
FAN Connector
The TEI0022 board offers one FAN connector for cooling the FPGA device. Depending on the assembly 5 V or 12 V are usable.
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Connector
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Connected to
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FAN_EN,
(High Side Switch U55, Pin 3)
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Several VCCIO voltages are available on the FMC connector to operate the I/O's on different voltage levels:
SMA Connector
The TEI0022 board offers seven SMA connectors for trigger and clock input and output.
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SMA Connector Signal Schematic Names | Connected to
J7 | SMA_CLK_OUT_p | Clock Generator U3, Pin 22 | J10 | SMA_CLK_OUT_n | Clock Generator U3, Pin 21 | J8 | TRIGGER_OUTPUT | Intel Cyclone V U10, Pin AE29 | J9 | TRIGGER_INPUT | Intel Cyclone V U10, Pin AA26 | J15 EXT_CLK_INPUT | Intel Cyclone V U10, Pin Y26 | J17 | CLK_INPUT | Intel Cyclone V U10, Pin AA26 | J18 | SMA_CLK_IN | Clock Generator U3, Pin 1 | |
SD Card Connector
SD Card connector J3 is connected to the Intel Cyclone V.
On-board Peripherals
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FAN Connector
The TEI0022 board offers one FAN connector for cooling the FPGA device. Depending on the assembly 5 V or 12 V are usable.
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SMA Connector
The TEI0022 board offers seven SMA connectors for trigger and clock input and output.
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Chip/Interface | Designator
System Controller Intel MAX10 | U41 | Intel Cyclone V | U10 | DDR3 SDRAM | U26...29 | Gigabit Ethernet PHY | U1 | High-Speed USB ULPI PHY | U8 | 4-Port USB 2.0 Hub | U33 | SD Card | J3 | HDMI | U23 | JTAG | U21 | UART | U30 | DIP-Switches | S2, S7...8 | Buttons | S1, S3...5 | On-Board LEDs | D1...15, D17...23, D25 | Temperature Sensor | U16 | QSPI | U6, U15 | EEPROM | U31, U38 | Clock Sources | U48, U32, U34 | Programmable Clock Generator | U3 | Power Monitoring | U54 | |
Temperatur Sensor
The temperature sensor ADT7410 (U16) is implemented on the TEI0022 board.
UART Interface
A UART connection between the USB B connector J5 and the Intel Cyclone HPS U10 is possible via the FT234XD (U30) chip.
Quad SPI Flash Memory
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SD Card Connector
SD Card connector J3 is connected to the Intel Cyclone V.
On-board Peripherals
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
Two 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron MT25QL256ABA8E12, U6, U15) are provided for FPGA and HPS configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA or the HPS allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.
Quad SPI Flash memory U6 is connected to the HPS bank 7B and U15 to FPGA bank 3A.
In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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| Signal Name | QSPI Flash Memory U6 Pin | FPGA Pin | ||||||||||||||||
| QSPI_CS/BOOTSEL1 | S#, Pin C2 | Bank 7B, Pin A18 | ||||||||||||||||
| QSPI_CLK | C, Pin B2 | Bank 7B, Pin D19 | ||||||||||||||||
| QSPI_DATA0 | DQ0, Pin D3 | Bank 7B, Pin C20 | ||||||||||||||||
| QSPI_DATA1 | DQ1, Pin D2 | Bank 7B, Pin H18 | ||||||||||||||||
| QSPI_DATA2 | DQ2, Pin C4 | Bank 7B, Pin A19 | ||||||||||||||||
| QSPI_DATA3 | DQ3, Pin D4 | Bank 7B, Pin E19 | ||||||||||||||||
| QSPI_RST | RST#, Pin A4 | Bank 7A, Pin E24 | ||||||||||||||||
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| Signal Name | QSPI Flash Memory U15 Pin | FPGA Pin | ||||||||||||||||
| nCSO | S#, Pin C2 | Bank 3A, Pin AB8 | ||||||||||||||||
| AS_DCK | C, Pin B2 | Bank 3A, Pin U7 | ||||||||||||||||
| AS_DATA0 | DQ0, Pin D3 | Bank 3A, Pin AE6 | ||||||||||||||||
| AS_DATA1 | DQ1, Pin D2 | Bank 3A, Pin AE5 | ||||||||||||||||
| AS_DATA2 | DQ2, Pin C4 | Bank 3A, Pin AE8 | ||||||||||||||||
| AS_DATA3 | DQ3, Pin D4 | Bank 3A, Pin AC7 | ||||||||||||||||
| AS_RST | RST#, Pin A4 | Bank 7A, Pin B22 |
Intel Cyclone V
The on TEI0022 board used Intel Cyclone V device is a SoC with integrated Arm-based HPS. The 5CSEMA5F31C8N version delivers one hard memory controller, 80K logic elements in an FineLineBGA (FBGA) with 896 pins for the commercial temperature range of TJ = 0...85 °C with speed grade eight.
Programmable Clock Generator
There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U3) to generate various reference clocks for the module.
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IN1
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IN3
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Reference input clock
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IN4
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IN5
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I²C interface muxed to Intel Cyclone V
Slave address: 0x70.
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I²C interface muxed to Intel Cyclone V
Slave address: 0x70.
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CLK0A/B
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SMA_CLK_OUT_p/n
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Clock to SMA connectors
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CLK1A/B
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System Controller Intel MAX10
The TEI0022 is equipped with an Intel MAX10 (U41) which is the central system management unit where essential control signals are logically linked by the implemented logic of the FPGA firmware. This generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and buttons between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller. Other tasks of the System Controller are the monitoring of the power-on sequence and configuration of the Intel Cyclone V FPGA. The functionalities and configuration of the pins depend on its firmware.
Intel Cyclone V
The on TEI0022 board used Intel Cyclone V device is a SoC with integrated Arm-based HPS. The 5CSEMA5F31C8N version delivers one hard memory controller, 80K logic elements in an FineLineBGA (FBGA) with 896 pins for the commercial temperature range of TJ = 0...85 °C with speed grade eight.
DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEI0022 SoM has one GByte volatile DDR3 SDRAM memory per FPGA (U26, U27) and HPS (U28, U29) for storing user application code and data.
- Part number: IS43TR16512BL-125KBLI
- Supply voltage: 1.35 V
- Speed: ???
- Temperature: TC = -40 °C up to 95 °C
Gigabit Ethernet PHY
On-board Gigabit Ethernet PHY (U1) is provided with Analog Devices ADIN1300. The Ethernet PHY RGMII interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V. The reference clock input of the PHY is supplied from the on-board 25.0 MHz oscillator (U48).
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High-Speed USB ULPI PHY
USB PHY (U8) is provided by USB3320C from Microchip. The ULPI interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V and PHY reference clock input is supplied from the on-board 24.0 MHz oscillator (U34).
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4-Port USB 2.0 Hub
On the TEI0022 board there are up to four USB 2.0 Hi-Speed ports available (J2, J12). The USB 2.0 ports are provided by Microchip Cypress USB2514B 4-port USB 2.0 Hub controller (U33) which is connected to the USB PHY USB3320C (U8) connected to the Intel Cyclone V HPS via ULPI.
HDMI Connector
The TEI0022 board provides an HDMI interface routed to the Intel Cyclone FPGA (U10). The HDMI interface is created by the HDMI transmitter ADV7511 provided by Analog Devices. The HDMI transmitter is incorporated in conjunction with the HDMI protection circuit TI TPD12S016 for more signal robustness.
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JTAG Interface
The TEI0022 uses as JTAG interface the FT2232 (U21) chip. With this and the settings it is possible to access the Cyclone V programmable logic, the processing system, the Intel MAX10 and the FMC.
UART Interface
A UART connection between the USB B connector J5 and the Intel Cyclone HPS U10 is possible via the FT234XD (U30) chip.
DIP-Switches
There are three 4-bit DIP-switches present on the TEI0022 board to configure options and set parameters. The following section describes the functionalities of the particular switches.
DIP-Switch S2
The table below describes the functionalities of the switches of DIP-switch S2 at their single positions:
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DIP-Switch S7
The table below describes the functionalities of the switches of DIP-switch S7 at their single positions:
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Clock to Intel MAX10 bank 2
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CLK_B4A_p/n
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Clock to FPGA bank 4A
Oscillators
The FPGA module has following reference clocking source provided by an on-board oscillator:
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| title | Reference clock signals |
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I2C
The TEI0022 provides three independent I2C busses. One bus is used to connect the FMC I2C with the Intel Cyclone V HPS. The second bus is to connect the HDMI device to the Intel Cyclone V FPGA. The third bus is used to handle the other on-board I2C devices.
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| title | On-board peripherals' I2C-interfaces device slave addresses |
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System Controller Intel MAX10
The TEI0022 is equipped with an Intel MAX10 (U41) which is the central system management unit where essential control signals are logically linked by the implemented logic of the FPGA firmware. This generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and buttons between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller. Other tasks of the System Controller are the monitoring of the power-on sequence and configuration of the Intel Cyclone V FPGA. The functionalities and configuration of the pins depend on its firmware.
EEPROM
The TEI0022 board contains two EEPROMs for configuration and general user purposes.
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| EEPROM Model | I2C Address | Designator | Memory Density | Purpose | Notes | 24AA025E48T-I/OT | 0x50 | U38 | 2 KBit | Ethernet MAC | 93AA56BT-I/OT | - | U31 | 2 KBit | JTAG Configuration |
High-Speed USB ULPI PHY
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DIP-Switch S8
The table below describes the functionalities of the switches of DIP-switch S8 at their single positions:USB PHY (U8) is provided by USB3320C from Microchip. The ULPI interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V and PHY reference clock input is supplied from the on-board 24.0 MHz oscillator (U34).
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PHY Pin | Connected to
ULPI | Intel Cyclone V HPS (U10) | REFCLK | 24 MHz from on board oscillator (U34) | REFSEL[0..2] | High (3.3 V) | RESETB | Intel Cyclone V HPS (U10) | DP, DM | 4-port USB 2.0 Hub (U33) | CPEN | Not Connected. | VBUS | Pull-up to 5 V. | ID | Not Connected. | |
4-Port USB 2.0 Hub
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Buttons
There are four buttons present on the TEI0022 board. The following section describes the functionalities of the particular buttons. The final functionality is set by the management Intel MAX10.
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Board LEDs
The TEI0022 board is equipped with several LEDs to signal current states and activities. The functionality of the LEDs D11...14 are user LEDs. The LED D8 shows the Intel Cyclone V configuration progress. LEDs D15, D18...19 shows the UART connection and the other LEDs mentioned in the table are supply power status LEDs.
There are three 4-bit DIP-switches present on the TEI0022 board to configure options and set parameters. The following section describes the functionalities of the particular switches.
DIP-Switch S2
The table below describes the functionalities of the switches of DIP-switch S2 at their single positions:
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| S4-1 | HPS_SW1 is low | HPS_SW1 is high | User switch | |||||||||||||||
| S4-2 | HPS_SW2 is low | HPS_SW2 is high | User switch | |||||||||||||||
| S4-3 | FPGA_SW1 is low | FPGA_SW1 is high | User switch | |||||||||||||||
| S4-4 | FPGA_SW2 is low | FPGA_SW2 is high | User switch |
DIP-Switch S7
The table below describes the functionalities of the switches of DIP-switch S7 at their single positions:
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| anchor | Table_OBP_DIP_S7 |
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| title | DIP-switch S7 functionality description |
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DIP-Switch S8
The table below describes the functionalities of the switches of DIP-switch S8 at their single positions:
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| anchor | Table_OBP_DIP_S8 |
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| title | DIP-switch S8 functionality description |
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Temperatur Sensor
The temperature sensor ADT7410 (U16) is implemented on the TEI0022 board.
Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
Two 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron MT25QL256ABA8E12, U6, U15) are provided for FPGA and HPS configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA or the HPS allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.
Quad SPI Flash memory U6 is connected to the HPS bank 7B and U15 to FPGA bank 3A.
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EEPROM
The TEI0022 board contains two EEPROMs for configuration and general user purposes.
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Clock Sources
The FPGA module has following reference clocking source provided by an on-board oscillator:
On-Board LEDs
The TEI0022 board is equipped with several LEDs to signal current states and activities. The functionality of the LEDs D11...14 are user LEDs. The LED D8 shows the Intel Cyclone V configuration progress. LEDs D15, D18...19 shows the UART connection and the other LEDs mentioned in the table are supply power status LEDs.
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DDR3 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TEI0022 SoM has one GByte volatile DDR3 SDRAM memory per FPGA (U26, U27) and HPS (U28, U29) for storing user application code and data.
- Part number: IS43TR16512BL-125KBLI
- Supply voltage: 1.35 V
- Speed: ???
- Temperature: TC = -40 °C up to 95 °C
Gigabit Ethernet PHY
On-board Gigabit Ethernet PHY (U1) is provided with Analog Devices ADIN1300. The Ethernet PHY RGMII interface is connected to the Intel Cyclone V HPS. I/O voltage is fixed at 3.3 V. The reference clock input of the PHY is supplied from the on-board 25.0 MHz oscillator (U48).
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ETH | Signal Description | 7B | ETH_TXCK | RGMII Transmit Reference Clock | 7B | ETH_TXD0 | RGMII Transmit Data 0 | 7B | ETH_TXD1 | RGMII Transmit Data 1 | 7B | ETH_TXD2 | RGMII Transmit Data 2 | 7B | ETH_TXD3 | RGMII Transmit Data 3 | 7B | ETH_TXCTL RGMII Transmit Control | 7B | ETH_RXCK | RGMII Receive Reference Clock | 7B | ETH_RXD0 | RGMII Receive Data 0 | 7B | ETH_RXD1 | RGMII Receive Data 2 | 7B | ETH_RXD2 | RGMII Receive Data 3 | 7B | ETH_RXD3 | RGMII Receive Data 4 | 7B | ETH_RXCTL RGMII Receive Control | 7C | ETH_RST | Reset | 7B | ETH_MDC | Management Data Clock | 7B | ETH_MDIO | Management Data I/O | 7B | PHY_INT | Interrupt | |
HDMI Connector
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Programmable Clock Generator
There is a Silicon Labs I2C programmable quad PLL clock generator on-board (Si5338A, U3) to generate various reference clocks for the moduleThe TEI0022 board provides an HDMI interface routed to the Intel Cyclone FPGA (U10). The HDMI interface is created by the HDMI transmitter ADV7511 provided by Analog Devices. The HDMI transmitter is incorporated in conjunction with the HDMI protection circuit TI TPD12S016 for more signal robustness.
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| HDMI connector J11 | Signal Schematic Name | Connected to | Notes | |||||||||||||
| Pin 1, 3 | HDMI_TX2_P / HDMI_TX2_N | HDMI transmitter, Pin 43, 42 | also connected to HDMI protection circuit | |||||||||||||
| Pin 4, 6 | HDMI_TX1_P / HDMI_TX1_N | HDMI transmitter, Pin 40, 39 | also connected to HDMI protection circuit | |||||||||||||
| Pin 7, 9 | HDMI_TX0_P / HDMI_TX0_N | HDMI transmitter, Pin 36, 35 | also connected to HDMI protection circuit | |||||||||||||
| Pin 10, 12 | HDMI_TXC_P / HDMI_TXC_N | HDMI transmitter, Pin 33, 32 | also connected to HDMI protection circuit | |||||||||||||
| Pin 13 | CEC_B | HDMI transmitter, Pin 48 | HDMI CEC, wired through HDMI protection circuit | |||||||||||||
| Pin 15 | SCL_B | HDMI transmitter, Pin 53 | HDMI I²C clock line, wired through HDMI protection circuit | |||||||||||||
| Pin 16 | SDA_B | HDMI transmitter, Pin 54 | HDMI I²C data line, wired through HDMI protection circuit | |||||||||||||
| Pin 19 | HPD_B | HDMI transmitter, Pin 30 | Hot Plug Detect, wired through HDMI protection circuit | Pin 18 | 5V_HDMI | HDMI protection circuit, Pin 13 | 5V supply voltage, wired through HDMI protection circuit
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| Si5338A Pin | Signal Name / Description | Connected to | Direction | Notes |
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IN1 | SMA_CLK_IN | SMA J18, Pin 1 | Input | |
| IN2 | SMA_CLK_IN | SMA J18, Pin 2 | Input | |
IN3 | Reference input clock | U48, Pin 3 | Input | 25 MHz oscillator U48, SiT8208 |
IN4 | - | GND | Input | I2C slave device address LSB |
IN5 | - | Not Connected | Input | Not used |
| IN6 | - | GND | Input | Not used |
| SCL | HPS_I2C_SCL | HPS I2C Bus U10, Pin H23 | Input | I²C interface muxed to Intel Cyclone V Slave address: 0x70. |
| SDA | HPS_I2C_SDA | HPS I2C Bus U10, Pin A25 | Input / Output | I²C interface muxed to Intel Cyclone V Slave address: 0x70. |
CLK0A/B | SMA_CLK_OUT_p/n | SMA J7/J10 | Output | Clock to SMA connectors |
CLK1A/B | CLK_B3B_p/n | U10, Pin AF14/15 | Clock to FPGA bank 3B | |
| CLK2A | CLK_50MHz_MAX10 | U41, Pin H6 | Output | Clock to Intel MAX10 bank 2 |
| CLK2B | HPS_CLK2_25MHz | U10, Pin F25 | Output | Clock to HPS bank 7A |
| CLK3A/B | CLK_B4A_p/n | U10, Pin AA16/AB17 | Output | Clock to FPGA bank 4A |
Power Monitoring
The TEI0022 uses a precision supply monitor (U54) for three voltages. Therefore if one of the voltages browns out it should be realized and handled.
Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
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