Page History
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- Intel Cyclone V, U10
- DDR3 SDRAM, U26...27
- DDR3 SDRAM, U28...29
- FMC, J4
- PMOD, P1...4
- SD Card Connector, J3
- Ethernet PHY, U1
- RJ45 Connector, J1
- USB ULPI, U8
- USB HUB, U33
- USB Connector, J2, J12
- HDMI Transmitter, U23
- HDMI Connector, J11
- Intel MAX10, U41
- Micro USB to UART Interface, J5, U30
- USB to JTAG, U21FTDI
- Micro USB JTAG, J13
- SMA Connector
- Push Button, S1, S3...5
- LED
- 4-Bit DIP Switch, S2, S7...8
- 12 V Power Jack, J6
- Protection Circuit, U42
- DCDC, U45...46
- Quad DCDC, U47, U49
- Dual DCDC, U50, U56
- DCDC, U43
- DCDC, U2
- Clock Generator, U48
- Programmable Clock Generator, U3
- QSPI - FPGA PS, U6
- QSPI - FPGA PL, U15
- Temperature Sensor, U16
- EEPROM, U38
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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