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| Scroll Title |
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| anchor | Figure_OV_MC |
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| title | TEI0022 main components |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | true |
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| viewerToolbar | true |
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| |
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| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
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| revision | 34 |
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| diagramName | Figure_OV_MC |
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| simpleViewer | true |
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| width | |
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| links | auto |
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| tbstyle | top |
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| diagramWidth | 521 |
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...
| Scroll Title |
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| anchor | Table_OV_BP |
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| title | Boot process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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BOOTSEL[1..0] Signal State | DIP-switch S7 position | Boot Mode | Notes |
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00 | S7A - ON; S7B - ON | FPGA | Firmware depentend | | 01 | S7A - ON; S7B - OFF | SD | Firmware depentend | | 11 | S7A - OFF; S7B - OFF | SPI | Firmware depentend |
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| Scroll Title |
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| anchor | Table_OV_RST |
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| title | Reset process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Reset | Button | Note |
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HPS cold reset | S1 | Firmware dependent | | HPS warm reset | S3 | Firmware dependent | | FPGA reset | S4 | Firmware dependent |
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Signals, Interfaces and Pins
| Page properties |
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
|
JTAG Interface
FMC LPC Connector
The FMC (FPGA Mezzanine Card) connector J4 with low pin count (LPC) provides as an ANSI/VITA 57.1 standard a modular interface to the Intel Cyclone V FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.
The connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connectorAccording to the JTAGEN and JTAGSEL[1..0] pins the management Intel MAX10 (U41), the Intel Cyclone V HPS (U10), the Intel Cyclone V FPGA (U10) or the FMC (J4) can be accessed via the micro USB B connector J13.
| Scroll Title |
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| anchor | Table_SIP_JTGFMC |
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| title | JTAG pins connectionFMC connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAGSEL1 | JTAGSEL0 | JTAGSEL1 | JTAGSEL0 |
|---|
| X | X | ON | Intel MAX10 |
| ON | ON | OFF | Intel Cyclone V HPS |
| ON | OFF | OFF | Intel Cyclone V FPGA |
OFF | ON | OFF | FMC| FMC Signal | Intel Cyclone V Direction | I/O Signal Count (Single Ended/Differential) | Voltage Level | Notes |
|---|
| LA0...1 | RX | 4 / 2 | FMC_VADJ |
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| LA3, LA5, LA7, ..., LA33 | RX | 32 / 16 | FMC_VADJ |
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| LA2, LA4, LA6, ..., LA32 | TX | 32 / 16 | FMC_VADJ |
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| CLK0...1 | RX | 4 / 2 | FMC_VADJ |
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The FMC connector provides further interfaces like JTAG and I²C interfaces:
| Scroll Title |
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| anchor | FigureTable_SIP_OVFMC_JTAGInterfaces |
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| title | TEI0022-01 JTAGFMC connector pin-outs of available interfaces |
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| ignoredrawiobordertrueviewerToolbartruefitWindowfalsediagramDisplayNamelbox | true |
| revision | 1 |
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| diagramName | Figure_OC_JTAG |
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| simpleViewer | true |
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width | | links | auto |
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| tbstyle | top |
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| diagramWidth | 641 |
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| Scroll Only |
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 Image Removed
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I2C
The TEI0022 provides three independent I2C busses. One bus is used to connect the FMC I2C with the Intel Cyclone V HPS. The second bus is to connect the HDMI device to the Intel Cyclone V FPGA. The third bus is used to handle the other on-board I2C devices.
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| anchor | Table_OBP_I2C |
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| title | On-board peripherals' I2C-interfaces device slave addresses |
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| 1 | | sortEnabled | false |
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| cellHighlighting | true |
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| Interface | I/O Signal Count | Pin schematic Names / FMC Pins | Connected to | Notes |
|---|
| JTAG | 5 | FMC_TCK, Pin J4-D29 FMC_TMS, Pin J4-D33 FMC_TDI, Pin J4-D30 FMC_TDO, Pin J4- D31 FMC_TRST#, Pin J4- D34 | Intel MAX10 U41, Bank 3 | VCCIO: +3.3V | | I2C | 2 | FMC_SCL, Pin J4-C30 FMC_SDA, Pin J4-C31 | Intel MAX10 U41, Bank 3 and Intel Cyclone V U10, Bank 7A | I2C-lines pulled-up to +3.3V | | Control Lines | 2 | FMC_PRSNT_M2C#, Pin J4-H2 (pulled-up to +3.3V) FMC_PG_C2M, Pin J4-D1 (pulled-up to +3.3V) | Intel MAX10 U41, Bank 3 and Intel Cyclone V U10, Bank 5B | 'PG' = 'Power Good'-signal 'C2M' = carrier to (Mezzanine) module 'M2C' = (Mezzanine) module to carrier |
|
Several VCCIO voltages are available on the FMC connector to operate the I/O's on different voltage levels:
| Scroll Title |
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| anchor | Table_SIP_FMC_Voltage |
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| title | Available VCCIO voltages on FMC connector |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| VCCIO Schematic Name | FMC Connector J4 Pins | Notes |
|---|
| +12.0V_FMC | C35/C37 | extern 12V power supply | | +3.3V_FMC | D36/D38/D40/C39 | 3.3V peripheral supply voltage | | +3.3V | D32 | 3.3V peripheral supply voltage | | FMC_VADJ | H40/G39 | adjustable FMC VCCIO voltage, supplied by DC-DC converter U43 | | FMC_VREF_A_M2C | H1 | adjustable reference voltage |
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| anchor | Figure_OV_I2C |
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| title | TEI0022-01 I2C |
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| Scroll Only |
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 Image Removed
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Pmod Connector
The TEI0022 board offers four Pmod (2x6 pins, SMD) connectors which provides as a standard modular interface single ended I/O pins for use with extension modules.
Following table gives an overview of the Pmod connectors and the signals routed to the attached Intel Cyclone V (U10):signals routed to the attached Intel Cyclone V (U10):
| Scroll Title |
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| anchor | Table_SIP_PMOD |
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| title | Pmod connectors pin description |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Pmod Connector P1 Pin | Signal Schematic Name | Connected to | Notes |
|---|
| 1 | P0_IO1 | Intel Cyclone V U10, Pin AD9 |
| | 2 | P0_IO2 | Intel Cyclone V U10, Pin AD11 |
| | 3 | P0_IO3 | Intel Cyclone V U10, Pin AD12 |
| | 4 | P0_IO4 | Intel Cyclone V U10, Pin AC12 |
| | 7 | P0_IO5 | Intel Cyclone V U10, Pin AC9 |
| | 8 | P0_IO6 | Intel Cyclone V U10, Pin AD10 |
| | 9 | P0_IO7 | Intel Cyclone V U10, Pin AA12 |
| | 10 | P0_IO8 | Intel Cyclone V U10, Pin AB12 |
| | Pmod Connector P2 |
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| Scroll Title |
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| anchor | Table_SIP_PMOD |
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| title | Pmod connectors pin description |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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style | widths | | sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Pmod Connector P1 | Pin | Signal Schematic Name | Connected to | Notes |
| 1 | P0P1_IO1 | Intel Cyclone V U10, Pin AD9X |
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| 2 | P0P1_IO2 | Intel Cyclone V U10, Pin AD11AF4 |
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| 3 | P0P1_IO3 | Intel Cyclone V U10, Pin | AD12AF8 |
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| 4 | P0P1_IO4 | Intel Cyclone V U10, Pin AC12AD7 |
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| 7 | P0P1_IO5 | Intel Cyclone V U10, Pin AC9AG1 |
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| 8 | P0P1_IO6 | Intel Cyclone V U10, Pin AD10AF5 |
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| 9 | P0P1_IO7 | Intel Cyclone V U10, Pin AA12AE7 |
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| 10 | P0P1_IO8 | Intel Cyclone V U10, Pin AB12AE9 |
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| Pmod Connector P2 P3 Pin | Signal Schematic Name | Connected to | Notes |
| 1 | P1P2_IO1 | Intel Cyclone V U10, Pin XAH5 |
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| 2 | P1P2_IO2 | Intel Cyclone V U10, Pin AF4AH3 |
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| 3 | P1P2_IO3 | Intel Cyclone V U10, Pin AF8AJ2 |
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| 4 | P1P2_IO4 | Intel Cyclone V U10, Pin AD7AG3 |
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| 7 | P1P2_IO5 | Intel Cyclone V U10, Pin AG1AG5 |
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| 8 | P1P2_IO6 | Intel Cyclone V U10, Pin AF5AH4 |
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| 9 | P1P2_IO7 | Intel Cyclone V U10, Pin AE7AH2 |
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| 10 | P1P2_IO8 | Intel Cyclone V U10, Pin AE9AJ1 |
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| Pmod Connector P3 P4 Pin | Signal Schematic Name | Connected to | Notes |
| 1 | P2P3_IO1 | Intel Cyclone V U10, Pin AH5AE12 |
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| 2 | P2P3_IO2 | Intel Cyclone V U10, Pin AH3AF9 |
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| 3 | P2P3_IO3 | Intel Cyclone V U10, Pin AJ2AG8 |
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| 4 | P2P3_IO4 | Intel Cyclone V U10, Pin AG3AG6 |
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| 7 | P2P3_IO5 | Intel Cyclone V U10, Pin AG5AE11 |
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| 8 | P2P3_IO6 | Intel Cyclone V U10, Pin AH4AF10 |
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| 9 | P2P3_IO7 | Intel Cyclone V U10, Pin AH2AG7 |
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| 10 | P2P3_IO8 | Intel Cyclone V U10, Pin | AJ1AF6 |
| Pmod Connector P4 Pin | Signal Schematic Name | Connected to | Notes |
1 | P3_IO1 | Intel Cyclone V U10, Pin AE12 | 2 | P3_IO2 | Intel Cyclone V U10, Pin AF9 | 3 | P3_IO3 | Intel Cyclone V U10, Pin AG8 | 4 | P3_IO4
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SMA Connector
The TEI0022 board offers up to seven SMA connectors for trigger and clock input and output.
| Scroll Title |
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| anchor | Table_SIP_SMA |
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| title | SMA connectors |
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| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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SMA Connector | Signal Schematic Names | Connected to | Notes |
|---|
| J7 | SMA_CLK_OUT_p | Clock Generator U3, Pin 22 | Assembly option | | J10 | SMA_CLK_OUT_n | Clock Generator U3, Pin 21 | Assembly option | | J8 | TRIGGER_OUTPUT | Intel Cyclone V U10, Pin |
AG67P3IO5| INPUT | Intel Cyclone V U10, Pin |
AE118P3IO6| INPUT | Intel Cyclone V U10, Pin |
AF109P3IO7| INPUT | Intel Cyclone V U10, Pin |
AG710P3IO8Intel Cyclone V U10, Pin AF6 | |
FMC LPC Connector
The FMC (FPGA Mezzanine Card) connector J4 with low pin count (LPC) provides as an ANSI/VITA 57.1 standard a modular interface to the Intel Cyclone V FPGA and exposes numerous of its I/O pins for use by other mezzanine modules and expansion cards.
| IN | Clock Generator U3, Pin 1 | Assembly option |
|
FAN Connector
The TEI0022 board offers one FAN connector for cooling the FPGA device. Depending on the assembly 5 V or 12 V are usableThe connector supports single ended (VCCIO: FMC_VADJ) and differential signaling as the I/O's are routed from the FPGA banks as LVDS-pairs to the FMC connector.
| Scroll Title |
|---|
| anchor | Table_SIP_FMCFAN |
|---|
| title | FMC FAN connectors information |
|---|
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| Scroll Table Layout |
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| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
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| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
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| cellHighlighting | true |
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| FMC Signal | Intel Cyclone V Direction | I/O Signal Count (Single Ended/Differential) | Voltage Level | Notes |
|---|
LA0...1 | RX | 4 / 2 | FMC_VADJ | LA3, LA5, LA7, ..., LA33 | RX | 32 / 16 | FMC_VADJ | LA2, LA4, LA6, ..., LA32 | TX | 32 / 16 | FMC_VADJ | CLK0...1 | RX | 4 / 2 | FMC_VADJ | Connector | Signal Schematic Names | Connected to | Notes |
|---|
| 2-Pin FAN Connector J16, 5 V or 12 V power supply depending on R270/271 with BTS4141N High Side Switch | FAN_EN, (High Side Switch U55, Pin 3) | Intel MAX10 U41, Pin C1 | Intel Cyclone V cooling FAN |
Micro USB Connector (JTAG)
The FMC connector provides further interfaces like JTAG and I²C interfaces:According to the JTAGEN and JTAGSEL[1..0] pins the management Intel MAX10 (U41), the Intel Cyclone V HPS (U10), the Intel Cyclone V FPGA (U10) or the FMC (J4) can be accessed via the micro USB B connector J13.
| Scroll Title |
|---|
| anchor | Table_SIP_FMC_InterfacesJTG |
|---|
| title | FMC connector pin-outs of available interfacesJTAG pins connection |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
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| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
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| cellHighlighting | true |
|---|
|
|
| Interface | I/O Signal Count | Pin schematic Names / FMC Pins | Connected to | Notes |
|---|
| JTAG | 5 | FMC_TCK, Pin J4-D29 FMC_TMS, Pin J4-D33 FMC_TDI, Pin J4-D30 FMC_TDO, Pin J4- D31 FMC_TRST#, Pin J4- D34 | Intel MAX10 U41, Bank 3 | VCCIO: +3.3V |
| I2C | 2 | FMC_SCL, Pin J4-C30 FMC_SDA, Pin J4-C31 | Intel MAX10 U41, Bank 3 and Intel Cyclone V U10, Bank 7A | I2C-lines pulled-up to +3.3V |
| Control Lines | 2 | FMC_PRSNT_M2C#, Pin J4-H2 (pulled-up to +3.3V) FMC_PG_C2M, Pin J4-D1 (pulled-up to +3.3V) | Intel MAX10 U41, Bank 3 and Intel Cyclone V U10, Bank 5B | 'PG' = 'Power Good'-signal 'C2M' = carrier to (Mezzanine) module 'M2C' = (Mezzanine) module to carrier |
...
JTAGSEL1 | JTAGSEL0 | JTAGSEL1 | JTAGSEL0 | Note |
|---|
| X | X | ON | Intel MAX10 |
| | ON | ON | OFF | Intel Cyclone V HPS | Firmware dependent | | ON | OFF | OFF | Intel Cyclone V FPGA | Firmware dependent | | OFF | ON | OFF | FMC | Firmware dependent |
|
| Scroll Title |
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| anchor | TableFigure_SIPOV_FMC_VoltageJTAG |
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| title | Available VCCIO voltages on FMC connectorTEI0022-01 JTAG |
|---|
|
tablelayout |
| orientation | portrait |
|---|
| sortDirection | ASC |
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| repeatTableHeaders | default |
|---|
style | widths | | sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
| VCCIO Schematic Name | FMC Connector J4 Pins | Notes |
|---|
| +12.0V_FMC | C35/C37 | extern 12V power supply |
| +3.3V_FMC | D36/D38/D40/C39 | 3.3V peripheral supply voltage |
| +3.3V | D32 | 3.3V peripheral supply voltage |
| FMC_VADJ | H40/G39 | adjustable FMC VCCIO voltage, supplied by DC-DC converter U43 |
| FMC_VREF_A_M2C | H1 | adjustable reference voltage |
FAN Connector
| ignore |
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| draw.io Diagram |
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| border | true |
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| viewerToolbar | true |
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| |
|---|
| fitWindow | false |
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| diagramDisplayName | |
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| lbox | true |
|---|
| revision | 1 |
|---|
| diagramName | Figure_OC_JTAG |
|---|
| simpleViewer | true |
|---|
| width | |
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| links | auto |
|---|
| tbstyle | top |
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| diagramWidth | 641 |
|---|
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| Scroll Only |
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Image Added |
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Micro USB Connector (UART)
A UART connection between the USB B connector J5 and the Intel Cyclone HPS U10 is possible via the FT234XD (U30) chip.
USB Connector
On the TEI0022 board there are up to four USB 2.0 Hi-Speed ports available (J2, J12).
HDMI Connector
The TEI0022 provides an HDMI Connector.
SD Card Connector
SD Card connector J3 is connected to the Intel Cyclone V.
RJ45 Connector
The board TEI0022 provides an ethernet interface via the RJ45 connector J1.
I2C
The TEI0022 provides three independent I2C busses. One bus is used to connect the FMC I2C with the Intel Cyclone V HPS. The second bus is to connect the HDMI device to the Intel Cyclone V FPGA. The third bus is used to handle the other on-board I2C devicesThe TEI0022 board offers one FAN connector for cooling the FPGA device. Depending on the assembly 5 V or 12 V are usable.
| Scroll Title |
|---|
| anchor | Table_SIPOBP_FANI2C |
|---|
| title | FAN connectorsOn-board peripherals' I2C-interfaces device slave addresses |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
Connector | Signal Schematic Names | Connected to | Notes |
|---|
| 2-Pin FAN Connector J16, 5 V or 12 V power supply depending on R270/271 with BTS4141N High Side Switch | FAN_EN, (High Side Switch U55, Pin 3) | Intel MAX10 U41, Pin C1 | Intel Cyclone V cooling FAN |
SMA Connector
The TEI0022 board offers up to seven SMA connectors for trigger and clock input and output.
...
| anchor | Table_SIP_SMA |
|---|
| title | SMA connectors |
|---|
...
SMA Connector
...
Connected to
...
J15
...
SD Card Connector
...
| Bus | I2C Device | Designator | I2C Address | Schematic Names of I2C Bus Lines | Notes |
|---|
| HPS I2C | Temperature Sensor | 0x4A | U16 | HPS_I2C_SCL / HPS_I2C_SDA | 3.3 V reference voltage | | HPS I2C | Programmable Clock Generator | 0x70 | U3 | HPS_I2C_SCL / HPS_I2C_SDA | 3.3 V reference voltage | | HPS I2C | EEPROM | 0x50 | U38 | HPS_I2C_SCL / HPS_I2C_SDA | 3.3 V reference voltage | | HDMI I2C | HDMI | 0x72 | U23 | HPS_I2C_SCL / HPS_I2C_SDA | 3.3 V reference voltage | | HPS FMC I2C | FMC | 0x50 | J4 | FMC_SCL / FMC_SDA | 3.3 V reference voltage |
|
| Scroll Title |
|---|
| anchor | Figure_OV_I2C |
|---|
| title | TEI0022-01 I2C |
|---|
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| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | true |
|---|
| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
|---|
| diagramDisplayName | |
|---|
| lbox | true |
|---|
| revision | 3 |
|---|
| diagramName | Figure_OV_I2C |
|---|
| simpleViewer | true |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | top |
|---|
| diagramWidth | 561 |
|---|
|
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| Scroll Only |
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Image Added |
|
On-board Peripherals
| Page properties |
|---|
|
Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
|
...
| Scroll Title |
|---|
| anchor | Table_OBP |
|---|
| title | On board peripherals |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
|
System Controller Intel MAX10
...
The on TEI0022 board used Intel Cyclone V device is a SoC with integrated ArmARM-based HPS. The 5CSEMA5F31C8N version delivers one hard memory controller, 80K logic elements in an FineLineBGA (FBGA) with 896 pins for the commercial temperature range of TJ = 0...85 °C with speed grade eight.
...
- Part number: IS43TR16512BL-125KBLI
- Supply voltage: 1.35 5 V
- Speed: TBD
- Temperature: TC = -40 °C up to 95 °C
...
| Scroll Title |
|---|
| anchor | Table_OBP_ETH |
|---|
| title | Ethernet PHY to HPS connections |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Bank | Signal NameETH | Signal Description |
|---|
| 7B | ETH_TXCK | RGMII Transmit Reference Clock | | 7B | ETH_TXD0 | RGMII Transmit Data 0 | | 7B | ETH_TXD1 | RGMII Transmit Data 1 | | 7B | ETH_TXD2 | RGMII Transmit Data 2 | | 7B | ETH_TXD3 | RGMII Transmit Data 3 | | 7B | ETH_TXCTL | RGMII Transmit Control | | 7B | ETH_RXCK | RGMII Receive Reference Clock | | 7B | ETH_RXD0 | RGMII Receive Data 0 | | 7B | ETH_RXD1 | RGMII Receive Data 2 | | 7B | ETH_RXD2 | RGMII Receive Data 3 | | 7B | ETH_RXD3 | RGMII Receive Data 4 | | 7B | ETH_RXCTL | RGMII Receive Control | | 7C | ETH_RST | Reset | | 7B | ETH_MDC | Management Data Clock | | 7B | ETH_MDIO | Management Data I/O | | 7B | PHY_INT | Interrupt |
|
...
On the TEI0022 board there are up to four USB 2.0 Hi-Speed ports available (J2, J12). The USB 2.0 ports are provided by Microchip Cypress USB2514B 4-port USB 2.0 Hub controller (U33) which is connected to the USB PHY USB3320C (U8) connected to the Intel Cyclone V HPS via ULPI.
HDMI
...
Transmitter
The TEI0022 board provides an HDMI interface routed to the Intel Cyclone FPGA (U10). The HDMI interface is created by the HDMI transmitter ADV7511 provided by Analog Devices. The HDMI transmitter is incorporated in conjunction with the HDMI protection circuit TI TPD12S016 for more signal robustness.
| Scroll Title |
|---|
| anchor | Table_OBP_HDMI |
|---|
| title | HDMI connector signals and pins |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| HDMI connector J11 | Signal Schematic Name | Connected to | Notes |
|---|
| Pin 1, 3 | HDMI_TX2_P / HDMI_TX2_N | HDMI transmitter, Pin 43, 42 | also connected to HDMI protection circuit | | Pin 4, 6 | HDMI_TX1_P / HDMI_TX1_N | HDMI transmitter, Pin 40, 39 | also connected to HDMI protection circuit | | Pin 7, 9 | HDMI_TX0_P / HDMI_TX0_N | HDMI transmitter, Pin 36, 35 | also connected to HDMI protection circuit | | Pin 10, 12 | HDMI_TXC_P / HDMI_TXC_N | HDMI transmitter, Pin 33, 32 | also connected to HDMI protection circuit | | Pin 13 | CEC_B | HDMI transmitter, Pin 48 | HDMI CEC, wired through HDMI protection circuit | | Pin 15 | SCL_B | HDMI transmitter, Pin 53 | HDMI I²C clock line, wired through HDMI protection circuit | | Pin 16 | SDA_B | HDMI transmitter, Pin 54 | HDMI I²C data line, wired through HDMI protection circuit | | Pin 19 | HPD_B | HDMI transmitter, Pin 30 | Hot Plug Detect, wired through HDMI protection circuit | | Pin 18 | 5V_HDMI | HDMI protection circuit, Pin 13 | 5V supply voltage, wired through HDMI protection circuit |
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JTAG Interface
The TEI0022 uses as JTAG interface the FT2232 (U21) chip. With this and the settings it is possible to access the Cyclone V programmable logic, the processing system, the Intel MAX10 and the FMC.
UART Interface
FTDI (JTAG)
Please refer to the section "Micro USB Connector (JTAG)".
FTDI (UART)
Please refer to the section "Micro USB Connector (UART)"A UART connection between the USB B connector J5 and the Intel Cyclone HPS U10 is possible via the FT234XD (U30) chip.
DIP-Switches
There are three 4-bit DIP-switches present on the TEI0022 board to configure options and set parameters. The following section describes the functionalities of the particular switches.
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| Scroll Title |
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| anchor | Table_OBP_DIP_S7 |
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| title | DIP-switch S7 functionality description |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| DIP-switch S7 | Position ON | Position OFF | Notes |
|---|
| S7-1 | HPS_SPI_SS/BOOTSEL0 is low | HPS_SPI_SS/BOOTSEL0 is high | Boot select (Firnware dependent) | | S7-2 | QSPI_CS/BOOTSEL1 is low | QSPI_CS/BOOTSEL1 is high | Boot select (Firnware dependent) | | S7-3 | JTAGSEL0 is low | JTAGSEL0 is high | JTAG select (Firnware dependent) | | S7-4 | JTAGSEL1 is low | JTAGSEL1 is high | JTAG select (Firnware dependent) |
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DIP-Switch S8
The table below describes the functionalities of the switches of DIP-switch S8 at their single positions:
| Scroll Title |
|---|
| anchor | Table_OBP_DIP_S8 |
|---|
| title | DIP-switch S8 functionality description |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| DIP-switch S8 | Position ON | Position OFF | Notes |
|---|
| S8-1 | JTAGEN is high | JTAGEN is low | JTAG select | | S8-2 | VID0_SW is low | VID0_SW is high | FMC_VADJ selection (Firnware dependent) | | S8-3 | VID1_SW is low | VID1_SW is high | FMC_VADJ selection (Firnware dependent) | | S8-4 | VID2_SW is low | VID2_SW is high | FMC_VADJ selection (Firnware dependent) |
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Buttons
There are four buttons present on the TEI0022 board. The following section describes the functionalities of the particular buttons. The final functionality is set by the management Intel MAX10.
| Scroll Title |
|---|
| anchor | Table_OBP_DIP_Buttons |
|---|
| title | Buttons functionality description |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Button | Position ON | Position OFF | Notes |
|---|
| S1 | HPS_RST#_SW is high | HPS_RST#_SW is low | Reset (cold) the Intel Cyclone V HPS (Firnware dependent) | | S3 | HPS_WARM_RST#_SW is high | HPS_WARM_RST#_SW is low | Reset (warm) the Intel Cyclone V HPS (Firnware dependent) | | S4 | FPGA_RST#_SW is high | FPGA_RST#_SW is low | Reset the Intel Cyclone V FPGA (Firnware dependent) | | S5 | USER_BTN_SW is high | USER_BTN_SW is low | User button (Firnware dependent) |
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On-Board LEDs
The TEI0022 board is equipped with several LEDs to signal current states and activities. The functionality of the LEDs D11...14 are user LEDs. The LED D8 shows the Intel Cyclone V configuration progress. LEDs D15, D18...19 shows the UART connection and the other LEDs mentioned in the table are supply power status LEDs.
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| Scroll Title |
|---|
| anchor | Table_OBP_PLL |
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| title | Programmable quad PLL clock generator inputs and outputs |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Si5338A Pin | Signal Name / Description | Connected to | Direction | Notes |
|---|
IN1 | SMA_CLK_IN | SMA J18, Pin 1 | Input | Assembly option dependent | | IN2 | SMA_CLK_IN | SMA J18, Pin 2 | Input | Assembly option dependent | IN3 | Reference input clock | U48, Pin 3 | Input | 25 MHz oscillator U48, SiT8208 | IN4 | - | GND | Input | I2C slave device address LSB | IN5 | - | Not Connected | Input | Not used | | IN6 | - | GND | Input | Not used | | SCL | HPS_I2C_SCL | HPS I2C Bus U10, Pin H23 | Input | I²C interface muxed to Intel Cyclone V Slave address: 0x70. | | SDA | HPS_I2C_SDA | HPS I2C Bus U10, Pin A25 | Input / Output | I²C interface muxed to Intel Cyclone V Slave address: 0x70. | CLK0A/B | SMA_CLK_OUT_p/n | SMA J7/J10 | Output | Clock to SMA connectors (Assembly option dependent) | CLK1A/B | CLK_B3B_p/n | U10, Pin AF14/15 |
| Clock to FPGA bank 3B | | CLK2A | CLK_50MHz_MAX10 | U41, Pin H6 | Output | Clock to Intel MAX10 bank 2 | | CLK2B | HPS_CLK2_25MHz | U10, Pin F25 | Output | Clock to HPS bank 7A | | CLK3A/B | CLK_B4A_p/n | U10, Pin AA16/AB17 | Output | Clock to FPGA bank 4A |
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| Page properties |
|---|
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
The maximum power consumption of this board mainly depends on the design which is running on the FPGA. Intel provides a power estimator excel sheets to calculate power consumption.
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Power Supply
The maximum power consumption of this board mainly depends on the design which is running on the FPGA. Intel provides a power estimator excel sheets to calculate power consumption.
Power Consumption
| Scroll Title |
|---|
| anchor | Table_PWR_PC |
|---|
| title | Power Consumption |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Power Input Pin | Typical Current |
|---|
| +12.0V_IN | TBD* |
|
* TBD - To Be Determined
Power Distribution Dependencies
All on-board voltages of the TEI0022 are generated out of the extern applied 12 V power supply.
There are following dependencies how the initial 12V power supply is distributed to the on-board DC-DC converters, which power up further DCDC converters and the particular on-board voltages:
| Scroll Title |
|---|
| anchor | TableFigure_PWR_PCPD |
|---|
| title | Power ConsumptionDistribution |
|---|
|
tablelayout |
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
style | widths | | sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
| Power Input Pin | Typical Current |
|---|
| +12.0V_IN | TBD* |
* TBD - To Be Determined
Power Distribution Dependencies
All on-board voltages of the TEI0022 are generated out of the extern applied 12 V power supply.
| ignore |
|---|
| draw.io Diagram |
|---|
| border | true |
|---|
| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
|---|
| diagramDisplayName | |
|---|
| lbox | true |
|---|
| revision | 6 |
|---|
| diagramName | Figure_PWR_PD |
|---|
| simpleViewer | true |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | top |
|---|
| diagramWidth | 642 |
|---|
|
|
| Scroll Only |
|---|
 Image Added
|
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Power-On Sequence
The following figures delivers the power-on sequence information. The figure Power Sequency shows the connections between the power devices and its management. The figure Suggested Power Sequency shows the recommended firmware power-on sequence.There are following dependencies how the initial 12V power supply is distributed to the on-board DC-DC converters, which power up further DCDC converters and the particular on-board voltages:
| Scroll Title |
|---|
| anchor | Figure_PWR_PDPS |
|---|
| title | Power DistributionSequency |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | true |
|---|
| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
|---|
| diagramDisplayName | |
|---|
| lbox | true |
|---|
| revision | 56 |
|---|
| diagramName | Figure_PWR_PDPS |
|---|
| simpleViewer | true |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | top |
|---|
| diagramWidth | 641511 |
|---|
|
|
| Scroll Only |
|---|
Image Removed |
|
...
 Image Added
|
|
| Scroll Title |
|---|
| anchor | Figure_PWR_PS_Suggested |
|---|
| title | Suggested Power Sequency |
|---|
|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | true |
|---|
| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
|---|
| diagramDisplayName | |
|---|
| lbox | true |
|---|
| revision | 42 |
|---|
| diagramName | Figure_PWR_PS_Suggested |
|---|
| simpleViewer | true |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | top |
|---|
| diagramWidth | 641547 |
|---|
|
|
| Scroll Only |
|---|
Image Removed Image Added |
|
Voltage Monitor Circuit
...
| Scroll Title |
|---|
| anchor | Table_PWR_BV |
|---|
| title | Intel Cyclone V SoC bank voltages. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Schematic Name | | Notes |
|---|
| Bank 3A | +3.3V | +3.3 V |
| | Bank 3B | VDD_DDR_FPGA | +1.5 V |
| | Bank 4A | VDD_DDR_FPGA | +1.5 V |
| | Bank 5A | +3.3V | +3.3 V |
| | Bank 5B | +3.3V | +3.3 V |
| | Bank 6A | VDD_DDR_HPS | +1.5 V |
| | Bank 6B | VDD_DDR_HPS | +1.5 V |
| | Bank 7A | +3.3V | +3.3 V |
| | Bank 7B | +3.3V | +3.3 V |
| | Bank 7C | +3.3V | +3.3 V |
| | Bank 7D | +3.3V | +3.3 V |
| | Bank 8A | FMC_VADJ | +3.3 V, +2.5 V, +1.8 V, +1.25 V, +1. |
2V, 2 V | Adjustable voltage (+0.8 V is not usable at the Intel Cyclone V) |
Adjustable voltage |
|
Technical Specifications
Absolute Maximum Ratings
...
| Scroll Title |
|---|
| anchor | Table_TS_ROC |
|---|
| title | Recommended operating conditions. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Parameter | Min | Max | Units | Reference Document |
|---|
| +12.0V_IN | 10.5 | 13 | V | Input power protection U42 |
|
Physical Dimensions
Module size: 160 mm × 130 mm. Please download the assembly diagram for exact numbers.
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