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Scroll Title
anchorFigure_OV_BD
titleTEBA0714 block diagram


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anchorTable_SIP_JTG
titleJTAG pins connection

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XMOD Header PinB2B ConnectorConnected toNote
AJM2-97B14_L25UART Transfer
BJM2-99B14_L0UART Receive
EJM2-100BOOTMODE
GJM1-94PROG_B
CJM1-90TCK
DJM1-86TDI
FJM1-88TDO
HJM1-92TMS
3.3VJM1-97,993.3V
VIOJM2-53V_CFG

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The DIP-switch S2 on Xmod Adapter TE0790 must be set as the following table.

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titleSFP+ Connector InformationJTAG pins connection

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Pin
S2
Connected to
ON
Notes
OFF
VCCR
Default
3.3V
Description
1Normal modeAdapter board CPLD update modeONUpdate Mode JTAG access to SC CPLD only
2Do not use (illegal setting)Normal modeOFFMust be in OFF state always.
3VIO connected to 3.3VPower VIO from pin header J2OFFUser I/O Voltage
4Power 3.3V from USBPower 3.3V from pin header J2OFFPower on-board peripherals (FTDI chip & SC CPLD, ...)


The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) should be configured by the DIP-switches S2-3 and S2-4 as the following.

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titleJTAG pins connection

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S2-3S2-43.3V (VCC) Pin 5VIO Pin 6Description
OFFOFF3.3V from base (input**)VIO from base (input**)3.3V (pin 5) and VIO (pin 6) sourced from base
OFFON3.3V from USB* (output**)VIO from base (input**)VIO sourced from base by Pin 6
ONOFF3.3V from base (input**)3.3V from base (input**)VIO and 3.3V source by base (Pin 5 and Pin 6 are shorted and both must be sourced by 3.3V)
ONON3.3V from USB* (output**)3.3V from USB* (output**)

3.3V (pin 5) and VIO (pin 6) sourced USB (Pin 5 and Pin 6 are shorted and both are 3.3V)


SFP+ Connector

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titleSFP+ Connector Information

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PinConnected toNotes
VCCR3.3V
VCCT3.3V
VREFGND
TD+/TD-VCCT3.3VVREFGNDTD+/TD-MGT TXMGT Lane
RD+/RD-MGT RXMGT Lane
TX/FAULTSFP0_TX_FAULSFP_CTRL
TX/DISABLESFP0_TX_DISSFP_CTRL
MOD-DEF2SFP0_SDASFP_CTRL
MOD-DEF1SFP0_SCLSFP_CTRL
MOD-DEF0SFP0_MT_DEF0SFP_CTRL
RS0/RS1SFP0_RS0_1SFP_CTRL
LOSSFP0_LOSSFP_CTRL


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titleOn-board LEDs

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DesignatorColorConnected toActive LevelNote
D1GreenGLEDActive LowHigh
D2RedRLEDActive High
D3RedDONEActive HighLow


Power and Power-On Sequence

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