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anchor	Table_SIP_XMODS2
title	JTAG pins connection

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OFF

S2ON	Status	DescriptionDefault	Notes	Description
1	Normal mode	Adapter board CPLD update mode	ON	Update Mode JTAG access to SC CPLD only
2Do not use (illegal setting)	Normal mode	OFF	Must be in OFF state always.
3	VIO connected to 3.3V	Power VIO from pin header J2	OFF	User I/O Voltage
4	Power 3.3V from USB	Power 3.3V from pin header J2	OFF	Power on-board peripherals (FTDI chip & SC CPLD, ...)

The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) should be configured by the DIP-switches S2-3 and S2-4 as the following.

ON	3.3V output from USB
4	OFF	VIO sourced from base by Pin 6

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anchor	Table_SIP_XMODS3/4
title	JTAG pins connection

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S2-3	S2-4	3.3V (VCC) Pin 5	VIO Pin 6	Description
OFF	OFF	3.3V from base (input**)	VIO from base (input**)	3.3V (pin 5) and VIO (pin 6) sourced from base
OFF	ON	3.3V from USB* (output**)	VIO from base (input**)	VIO sourced from base by Pin 6
ON	OFF	3.3V from base (input**)	3.3V from base (input**)	VIO and 3.3V source by base (Pin 5 and Pin 6 are shorted and both must be sourced by 3.3V)
ON	ON	3.3V from USB* (output**)	3.3V from USB* (output**)	3.3V (pin 5) and VIO (pin 6) sourced USB (Pin 5 and Pin 6 are shorted and both are 3.3V)

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