Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Scroll Title
anchorTable_OV_IDS
titleInitial delivery state of programmable devices on the module

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Storage device name

Content

Notes

HPS SPI Flash (U6)

Not programmed

HPS Configuration

FPGA SPI Flash (U15)Not programmedFPGA Configuration
MAC EEPROM (U38)Not Programmed

MAC programmed, otherwise not programmed

Ethernet MAC

FTDI EEPROM (U31)ProgrammedFTDI Functionality


...

Scroll Title
anchorTable_OV_BP
titleBoot process.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Firmware dependent

BOOTSEL[1..0] Signal State

DIP-switch S7 positionBoot ModeNotes

00

S7A - ON; S7B - ON

FPGA


01S7A - ON; S7B - OFFSDFirmware dependent
11S7A - OFF; S7B - OFFSPIFirmware dependent




Scroll Title
anchorTable_OV_RST
titleReset process.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Reset

ButtonNote

HPS cold reset

S1Firmware dependent
HPS warm resetS3Firmware dependent
FPGA resetS4Firmware dependent


Signals, Interfaces and Pins

...

Scroll Title
anchorTable_SIP_PMOD
titlePmod connectors pin description

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Pmod Connector P1 PinSignal Schematic NameConnected to Intel Cyclone V, U10Notes
1P0_IO1
Intel Cyclone V U10,
Pin AD9
2P0_IO2
Intel Cyclone V U10,
Pin AD11
3P0_IO3
Intel Cyclone V U10,
Pin AD12
4P0_IO4
Intel Cyclone V U10,
Pin AC12
7P0_IO5
Intel Cyclone V U10,
Pin AC9
8P0_IO6
Intel Cyclone V U10,
Pin AD10
9P0_IO7
Intel Cyclone V U10,
Pin AA12
10P0_IO8
Intel Cyclone V U10,
Pin AB12
Pmod Connector P2 PinSignal Schematic NameConnected to Intel Cyclone V, U10Notes
1P1_IO1
Intel Cyclone V U10,
Pin
X
AG2
2P1_IO2
Intel Cyclone V U10,
Pin AF4
3P1_IO3
Intel Cyclone V U10,
Pin AF8
4P1_IO4
Intel Cyclone V U10,
Pin AD7
7P1_IO5
Intel Cyclone V U10,
Pin AG1
8P1_IO6
Intel Cyclone V U10, Pin
Pin AF5
9P1_IO7
Intel Cyclone V U10,
Pin AE7
10P1_IO8
Intel Cyclone V U10,
Pin AE9
Pmod Connector P3 PinSignal Schematic NameConnected to Intel Cyclone V, U10Notes
1P2_IO1
Intel Cyclone V U10,
Pin AH5
2P2_IO2
Intel Cyclone V U10,
Pin AH3
3P2_IO3
Intel Cyclone V U10,
Pin AJ2
4P2_IO4
Intel Cyclone V U10,
Pin AG3
7P2_IO5
Intel Cyclone V U10,
Pin AG5
8P2_IO6
Intel Cyclone V U10,
Pin AH4
9P2_IO7
Intel Cyclone V U10,
Pin AH2
10P2_IO8
Intel Cyclone V U10,
Pin AJ1
Pmod Connector P4 PinSignal Schematic NameConnected to Intel Cyclone V, U10Notes
1P3_IO1
Intel Cyclone V U10,
Pin AE12
2P3_IO2
Intel Cyclone V U10,
Pin AF9
3P3_IO3
Intel Cyclone V U10,
Pin AG8
4P3_IO4
Intel Cyclone V U10,
Pin AG6
7P3_IO5
Intel Cyclone V U10,
Pin AE11
8P3_IO6
Intel Cyclone V U10,
Pin AF10
9P3_IO7
Intel Cyclone V U10,
Pin AG7
10P3_IO8
Intel Cyclone V U10,
Pin AF6


SMA Connector

The TEI0022 board offers up to seven SMA connectors for trigger and clock input and output.

...

Scroll Title
anchorTable_SIP_JTG
titleJTAG pins connection

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

JTAGSEL1

JTAGSEL0

JTAGSEL1

JTAGSEL0Note
XXONIntel MAX10
ONONOFFIntel Cyclone V HPSFirmware dependent
ONOFFOFFIntel Cyclone V FPGAFirmware dependent
OFFONOFFFMCFirmware dependent



Scroll Title
anchorFigure_OV_JTAG
titleTEI0022-01 JTAG


Scroll Ignore

draw.io Diagram
bordertrue
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision1
diagramNameFigure_OC_JTAG
simpleViewertrue
width
linksauto
tbstyletop
diagramWidth641


Scroll Only


...