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Scroll Title |
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anchor | Table_OV_IDS |
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title | Initial delivery state of programmable devices on the module |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Storage device name | Content | Notes |
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HPS SPI Flash (U6) | Not programmed | HPS Configuration | FPGA SPI Flash (U15) | Not programmed | FPGA Configuration | MAC EEPROM (U38)Not | Programmed MAC programmed, otherwise not programmed | Ethernet MAC | FTDI EEPROM (U31) | Programmed | FTDI Functionality |
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Scroll Title |
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anchor | Table_OV_BP |
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title | Boot process. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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BOOTSEL[1..0] Signal State | DIP-switch S7 position | Boot Mode | Notes |
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00 | S7A - ON; S7B - ON | FPGA | Firmware dependent |
| 01 | S7A - ON; S7B - OFF | SD | Firmware dependent |
| 11 | S7A - OFF; S7B - OFF | SPI | Firmware dependent |
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Scroll Title |
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anchor | Table_OV_RST |
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title | Reset process. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Reset | Button | Note |
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HPS cold reset | S1 | Firmware dependent |
| HPS warm reset | S3 | Firmware dependent |
| FPGA reset | S4Firmware dependent |
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Signals, Interfaces and Pins
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Scroll Title |
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anchor | Table_SIP_PMOD |
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title | Pmod connectors pin description |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Pmod Connector P1 Pin | Signal Schematic Name | Connected to Intel Cyclone V, U10 | Notes |
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1 | P0_IO1 | Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Pin AB12 |
| Pmod Connector P2 Pin | Signal Schematic Name | Connected to Intel Cyclone V, U10 | Notes | 1 | P1_IO1 | Intel Cyclone V U10, XIntel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Pin Intel Cyclone V U10, Intel Cyclone V U10, Pin AE9 |
| Pmod Connector P3 Pin | Signal Schematic Name | Connected to Intel Cyclone V, U10 | Notes | 1 | P2_IO1 | Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Pin AJ1 |
| Pmod Connector P4 Pin | Signal Schematic Name | Connected to Intel Cyclone V, U10 | Notes | 1 | P3_IO1 | Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10, Intel Cyclone V U10,
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SMA Connector
The TEI0022 board offers up to seven SMA connectors for trigger and clock input and output.
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Scroll Title |
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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JTAGSEL1 | JTAGSEL0 | JTAGSEL1 | JTAGSEL0 | Note |
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X | X | ON | Intel MAX10 |
| ON | ON | OFF | Intel Cyclone V HPSFirmware dependent |
| ON | OFF | OFF | Intel Cyclone V FPGAFirmware dependent |
| OFF | ON | OFF | FMCFirmware dependent |
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Scroll Title |
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anchor | Figure_OV_JTAG |
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title | TEI0022-01 JTAG |
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Scroll Ignore |
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draw.io Diagram |
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border | true |
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viewerToolbar | true |
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| |
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fitWindow | false |
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diagramDisplayName | |
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lbox | true |
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revision | 1 |
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diagramName | Figure_OC_JTAG |
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simpleViewer | true |
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width | |
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links | auto |
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tbstyle | top |
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diagramWidth | 641 |
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|
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Scroll Only |
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