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Notes :

Add basic key futures, which can be tested with the design

Excerpt
Vivado 20182019.32 PetaLinux SD ETH (use EEPROM MAC) USB I2C RTC VIO PHY LED FSBL for EEPROM MAC and CPLD access Special FSBL for QSPI Programming

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Date	Vivado	Project Built	Authors	Description
2019-12-18	2019.2	TE0720-test_board-vivado_2019.2-build_1_20191218151902.zip TE0720-test_board_noprebuilt-vivado_2019.2-build_1_20191218152732.zip	John Hartfiel	2019.2 update Vitis support
2019-03-04	2018.3	TE0720-test_board-vivado_2018.3-build_01_20190304100745.zip TE0720-test_board_noprebuilt-vivado_2018.3-build_01_20190304100755.zip	John Hartfiel	update for -1CR version only (256MB DDR3)
2019-02-21	2018.3	TE0720-test_board-vivado_2018.3-build_01_20190221125123.zip TE0720-test_board_noprebuilt-vivado_2018.3-build_01_20190221125133.zip	John Hartfiel	TE Script update rework of the FSBLs some additional Linux features
2018-08-23	2018.2	te0720-test_board-vivado_2018.2-build_03_20180823185142.zip te0720-test_board_noprebuilt-vivado_2018.2-build_03_20180823185158.zip	John Hartfiel	DDR setup bugfix for l1if only
2018-08-13	2018.2	te0720-test_board-vivado_2018.2-build_02_20180810162024.zip te0720-test_board_noprebuilt-vivado_2018.2-build_02_20180810162040.zip	John Hartfiel	2018.2 update Boart Part Files rework
2018-04-26	2017.4	te0720-test_board-vivado_2017.4-build_07_20180426144351.zip te0720-test_board_noprebuilt-vivado_2017.4-build_07_20180426144405.zip	John Hartfiel	new assembly variant
2018-03-12	2017.4	te0720-test_board_noprebuilt-vivado_2017.4-build_06_20180312152408.zip te0720-test_board-vivado_2017.4-build_06_20180312152419.zip	John Hartfiel	add assembly variant script update
2018-01-09	2017.4	te0720-test_board_noprebuilt-vivado_2017.4-build_02_20180109121313.zip te0720-test_board-vivado_2017.4-build_02_20180109121300.zip	John Hartfiel	no design changes set EEPROM MAC with FSBL+u-boot FSBL for QSPI Programming
2017-11-27	2017.2	te0720-test_board_noprebuilt-vivado_2017.2-build_05_20171127153028.zip te0720-test_board-vivado_2017.2-build_05_20171127153006.zip	John Hartfiel	remove duplicated content
2017-11-20	2017.2	te0720-test_board_noprebuilt-vivado_2017.2-build_05_20171122074701.zip te0720-test_board-vivado_2017.2-build_05_20171122074646.zip	John Hartfiel	initial release

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Software	Version	Note
VivadoVitis	20182019.32	needed
SDK	2018.3	needed
Vivado is included into Vitis installation
PetaLinux	2019.2	PetaLinux	2018.3	needed

Hardware

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Notes :

list of software which was used to generate the design

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Type	Location	Notes
Vivado	<design name>/block_design <design name>/constraints <design name>/ip_lib	Vivado Project will be generated by TE Scripts
Vitis	SDK/HSI	<design name>/sw_lib	Additional Software Template for SDK/HSI Vitis and apps_list.csv with settings automatically for HSIVitis app generation
PetaLinux	<design name>/os/petalinux	PetaLinux template with current configuration

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prebuilt files

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File	File-Extension	Description
BIF-File	*.bif	File with description to generate Bin-File
BIN-File	*.bin	Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File	*.bit	FPGA (PL Part) Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Debian SD-Image	*.img	Debian Image for SD-Card
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdfxsa	Exported Vivado Hardware Specification for SDK/HSI Vitis and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
SREC-File	*.srec	Converted Software Application for MicroBlaze Processor Systems

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File	File-Extension	Description
BIF-File	*.bif	File with description to generate Bin-File
BIT-File	*.bit	FPGA (PL Part) Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Debian SD-Image	*.img	Debian Image for SD-Card
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdfxsa	Exported Vivado Hardware Specification for SDK/HSI Vitis and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

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Reference Design is available on:

TE0720 "Test Board" Reference Design

Design Flow

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Notes :

Basic Design Steps
Add/ Remove project specific description

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_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Press 0 and enter to start "Module Selection Guide"
(optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
  Note: Select correct one, see TE Board Part Files
Create HDF and export to prebuilt folder
1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
  Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
Create Linux (uboot.elf and image.ub) with exported HDFXSA
1. HDF XSA is exported to "prebuilt\hardware\<short name>"
  Note: HW Export from Vivado GUI create another path as default workspace.
2. Create Linux images on VM, see PetaLinux KICKstart
  1. Use TE Template from /os/petalinux
Add Linux files (uboot.elf and image.ub) to prebuilt folder
1. "prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
  Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\<DDR size>" of the selected device
Generate Programming Files with HSI/SDKVitis
- Run on Vivado TCL: TE::sw_run_
hsi
- vitis -all
  Note: Depending of PC performance this can take several minutes. Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" and open Vitis
- (alternative) Start
SDK
- Vitis with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_
sdk
- vitis
  Note:
See SDK Projects
- TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis

Launch

Programming

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Note:

Programming and Startup procedure

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Code Block

language	ruby
title	_i_TE0720-SC.xdc

#
# Constraints for System controller support logic
#
set_property PACKAGE_PIN K16 [get_ports PL_pin_K16]
set_property PACKAGE_PIN K19 [get_ports PL_pin_K19]
set_property PACKAGE_PIN K20 [get_ports PL_pin_K20]
set_property PACKAGE_PIN L16 [get_ports PL_pin_L16]
set_property PACKAGE_PIN M15 [get_ports PL_pin_M15]
set_property PACKAGE_PIN N15 [get_ports PL_pin_N15]
set_property PACKAGE_PIN N22 [get_ports PL_pin_N22]
set_property PACKAGE_PIN P16 [get_ports PL_pin_P16]
set_property PACKAGE_PIN P22 [get_ports PL_pin_P22]

#
# If Bank 34 is not 3.3V Powered need change the IOSTANDARD
#
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_P16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N22]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_N15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_M15]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_L16]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K20]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K19]
set_property IOSTANDARD LVCMOS33 [get_ports PL_pin_K16]

Software Design -

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Vitis

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Note:

optional chapter separate
sections for different apps

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For SDK project creation, follow instructions from:SDK Projects

Vitis

Application

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----------------------------------------------------------

FPGA Example

todo..

----------------------------------------------------------

Zynq Example:

zynq_fsbl

TE modified 2018.3 FSBL

General:

Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device ID

Module Specific:

Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY

zynq_fsbl_flash

TE modified 2018.3 FSBL

General:

Modified Files: main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2018.3 FSBL

General:

Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device Name

Module Specific:

Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2018.3 FSBL

General:

Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Template location: ./sw_lib/sw_apps/

zynq_fsbl

TE modified 20182019.3 2 FSBL

General:

Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device ID

...

zynq_fsbl_flash

TE modified 20182019.3 2 FSBL

General:

Modified Files: main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

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Code Block

language	js

#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000
#define DFU_ALT_INFO_RAM \
                "dfu_ram_info=" \
        "setenv dfu_alt_info " \
        "image.ub ram $netstart 0x1e00000\0" \
        "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
        "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"

#define DFU_ALT_INFO_MMC \
        "dfu_mmc_info=" \
        "set dfu_alt_info " \
        "${kernel_image} fat 0 1\\\\;" \
        "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
        "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"


/*Required for uartless designs */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
#ifdef CONFIG_DEBUG_UART
#undef CONFIG_DEBUG_UART
#endif
#endif

/*Define CONFIG_ZYNQ_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. Dependencies for ENV to be stored in EEPROM. Ensure environment fits in eeprom size*/
#ifdef CONFIG_ENV_ZYNQIS_IN_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN         1
#define CONFIG_SYS_I2C_EEPROM_ADDR             0x54
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS      4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS  5
#define CONFIG_SYS_EEPROM_SIZE                 1024 /* Bytes */
#define CONFIG_SYS_I2C_MUX_ADDR                0x74
#define CONFIG_SYS_I2C_MUX_EEPROM_SEL          0x4
#endif


#define CONFIG_PREBOOT    "echo U-BOOT for petalinux;echo importing env from FSBL shared area at 0xFFFFFC00; if itest *0xFFFFFC00 == 0xCAFEBABE; then echo Found valid magic; env import -t 0xFFFFFC04; fi;setenv preboot; echo; dhcp"

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CONFIG_i2c-tools=y
CONFIG_busybox-httpd=y (for web server app)
CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)

Applications

startup

Script App to load init.sh from SD Card if available.

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Date

Document Revision

Authors

Description

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	modified-date
	modified-date
dateFormat	yyyy-MM-dd

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	current-version
	current-version
prefix	v.

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	modified-user
	modified-user

2019.2 release

2019-12-03

v.34

John Hartfiel

bugfix document link

2019-10-28

v.33

John Hartfiel

removed remove instructions that are no longer used

2019-05-07

v.31

John Hartfiel

Some FSBL notes
wrong link

2019-03-06

v.28

John Hartfiel

Fixed prebuilt issue for TE0720-03-1CR

2019-03-01

v.27

John Hartfiel

Known issue for TE0720-03-1CR linux design

2019-02-21

v.26

John Hartfiel

2018.3 release finished (include design reworks)

2018-08-30

v.25

John Hartfiel

update documentation PS configuration

2018-08-23

v.24

John Hartfiel

update l1if boart parts

2018-08-13

v.23

John Hartfiel

2018.4 release

2018-04-26

v.22

John Hartfiel

add assembly variant

2018-02-20

v.20

John Hartfiel

small documentation update

2018-01-09

v.16

John Hartfiel

Release 2017.4
Documentation update

2017-11-27

v.14

John Hartfiel

Typo correction
Design Files update

2017-11-22

v.12

John Hartfiel

Update HW list

2017-11-22

v.11

John Hartfiel

Release 2017.2

2017-11-20

v.1

Page info

	created-user
	created-user

Initial release

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All

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	modified-users
	modified-users

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Trenz Electronic Documentation

Versions Compared

Old Version 34

New Version 35

Key

Hardware

Design Flow

Launch

Programming

Software Design -

Vitis

Application

zynq_fsbl

zynq_fsbl_flash

zynqmp_fsbl

zynqmp_fsbl_flash

zynqmp_pmufw

hello_te0820

u-boot

zynq_fsbl

zynq_fsbl_flash

Applications

startup