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Template Revision 2.6 7 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"

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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Vitis/Vivado 20182019.32
  • QSPI
  • SDK
  • Custom Carrier (minimum PS Design with available module components only)
  • Modified FSBL (some additional outputs only)
  • Special FSBL for QSPI Programming

...

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02082204201902071115392
DateVivadoProject BuiltAuthorsDescription
20192020-01-050222720182019.32TE0807-test_board_noprebuilt-vivado_20182019.32-build_054_2019052213240820200127075704.zip
TE0807-test_board-vivado_20182019.32-build_054_2019052213235620200127075454.zip		John Hartfiel
  • 2019.2 update
  • Vitis support
  • custom FSBL
  • Note: Prebuilt for ES2 version not included
2019-05-222018.3TE0807-test_board_noprebuilt-vivado_2018.3-build_05_20190522132408.zip
TE0807-test_board-vivado_2018.		3-build_05_20190522132356.zipJohn Hartfiel
  • custom FSBL
  • Note: Prebuilt for ES2 version not included
2019-02-082018.2TE0807-test_board_noprebuilt-vivado_2018.2-build_04_20190207111539.zip
TE0807-test_board-vivado_2018.2-build_04_04_20190207111524.zip		John Hartfiel
  • new assembly variant
2018-09-042018.2TE0807-test_board_noprebuilt-vivado_2018.2-build_03_20180904121458.zip
TE0807-test_board-vivado_2018.2-build_03_20180904121522.zip		John Hartfiel
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
2018-01-182017.4TE0807-test_board_noprebuilt-vivado_2017.4-build_05_20180118152119.zip
TE0807-test_board-vivado_2017.4-build_05_20180118152104.zip		John Hartfiel
  • rework Board Part Files

2017-11-14

2017.2TE0807-test_board_noprebuilt-vivado_2017.2-build_05_20171114115524.zip
TE0807-test_board-vivado_2017.2-build_05_20171114115511.zip		John Hartfiel
  • initial release


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titleSoftware

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SoftwareVersionNote
VivadoVitis20182019.32needed
SDK2018.3needed
, Vivado is included into Vitis installation


Hardware

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Notes :

  • list of software which was used to generate the design

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0807-01-07EV-ES   ES   es2_2gb      REV01    2GB      64GB       NA         NA     Slower DDR Speed Not longer supported by vivado
TE0807-02-07EV-1E   7ev_1e_4gb   REV02    4GB      64GB       NA         NA     NA            NA                               
TE0807-02-07EV-1EK  7ev_1e_4gb   REV02    4GB      64GB       NA         NA     with heat sink   

Note: Design contains also Board Part Files for TE0807+TEBF0808 configuration, this boart part files are not used for this reference design.

Design supports following carriers:

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titleHardware Carrier

...

sink                 
TE0807-02-4BE21-A   4eg_1e_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7DE21-A   7ev_1e_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7DI21-C   7ev_1i_4gb   REV02    4GB      128MB      NA         NA     without encryption             
TE0807-02-7DI21-A   7ev_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-4AI21-A   4cg_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-5AI21-A   5cg_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7AI21-A   7cg_1i_4gb   REV02    4GB      128MB      NA         NA     NA                               
TE0807-02-7DI24-A   7ev_1i_4gb   REV02    4GB      512MB      NA         NA     NA                               
TE0807-02-7DE21-AK  7ev_1e_4gb   REV02    4GB      128MB      NA         NA     with heat sink                 


Note: Design contains also Board Part Files for TE0807+TEBF0808 configuration, this boart part files are not used for this reference design.

Design supports following carriers:

Additional HW Requirements:

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anchorTable_AHW
titleAdditional Hardware

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Content

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  • content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx devices

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titleDesign sourcesHardware Carrier

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TypeLocationCarrier ModelNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib		Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI

...

Custom PCB use simple Board Part files, if MIO connected is different to TEBF0808
TEBF0808Used as reference carrier.
TEBT0808-01Change UART0 to UART1 (MIO68...69) and regenerate design


Additional HW Requirements:

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titleAdditional design sourcesHardware

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TypeAdditional HardwareLocationNotes
---------

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Content

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Notes :

  • prebuilt files
    • Template Table:
    • content of the zip file

    For general structure and of the reference design, see Project Delivery - Xilinx devices

    Design Sources

    PFPrebuilt files
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    title
    Design sources

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    File
    Type
    File-Extension
    Location
    Description
    Notes
    BIF-File*.bifFile with description to generate Bin-File
    BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
    BIT-File*.bitFPGA (PL Part) Configuration File
    DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

    Debian SD-Image

    *.img

    Debian Image for SD-Card

    Diverse Reports---Report files in different formats
    Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
    LabTools Project-File*.lprVivado Labtools Project File

    MCS-File

    *.mcs

    Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

    MMI-File

    *.mmi

    File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

    OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
    Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

    SREC-File

    *.srec

    Converted Software Application for MicroBlaze Processor Systems

    Vivado<design name>/block_design
    <design name>/constraints
    <design name>/ip_lib    		Vivado Project will be generated by TE Scripts
    Vitis<design name>/sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation


    Additional Sources

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    TypeLocationNotes
    ---------


    Prebuilt

    • prebuilt files
    • Template Table:


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    titlePrebuilt files (only on ZIP with prebult content)
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    File

    File-Extension

    Description

    BIF-File*.bifFile with description to generate Bin-File
    BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
    BIT-File*.bitFPGA (PL Part) Configuration File
    Diverse Reports---Report files in different formats
    Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
    LabTools Project-File*.lprVivado Labtools Project File
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    titlePrebuilt files

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    File

    File-Extension

    Description

    BIF-File*.bifFile with description to generate Bin-File
    BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
    BIT-File*.bitFPGA (PL Part) Configuration File
    DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

    Debian SD-Image

    *.img

    Debian Image for SD-Card

    Diverse Reports---Report files in different formats
    Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
    LabTools Project-File*.lprVivado Labtools Project File

    MCS-File

    *.mcs

    Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

    MMI-File

    *.mmi

    File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

    OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      • Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

    Download

    Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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    Reference Design is available on:

    Design Flow

    Page properties
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    Notes :

    • Basic Design Steps

    • Add/ Remove project specific description

    Note

    Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

    Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

    See also:

    The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

    TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

    1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
      Image Removed
    2. Press 0 and enter to start "Module Selection Guide"
    3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
    4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
      1. S(optional for manual changes)elect correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
        Note: Select correct one, see TE Board Part Files
         Important: Use Board Part Files, which did not ends with *_tebf0808
    5. Create HDF and export to prebuilt folder
      1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
        Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
    6. Generate Programming Files with HSI/SDK
      1. Run on Vivado TCL: TE::sw_run_hsi
        Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
      2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
        Note: See SDK Projects

    Launch

    Programming

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    • Programming and Startup procedure
    Note

    Check Module and Carrier TRMs for proper HW configuration before you try any design.

    Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

    QSPI

    1. Connect JTAG and power on carrier with module
    2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
    3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0807
      Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup

    Use SDK instead of Vivado is also possible, see: SDK Projects#Xilinx%22HelloWorld%22onZynqMP

    SD

    This does not work, because SD controller is not selected on PS.

    JTAG

    Load configuration and Application with SDK Debugger into device, see:

    Usage

    QSPI Boot:

    1. Prepare HW like described on section Programming
    2. Connect UART USB (most cases same as JTAG)
    3. Select QSPI Card as Boot Mode
      Note: See TRM of the Carrier, which is used.
    4. Power On PCB
      Note: 1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from QSPI into OCM, 2. FSBL loads Application into DDR

    Debugging:

    System Design - Vivado

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    • Description of Block Design, Constrains... BD Pictures from Export...

    Block Design

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    titleBlock Design
    Image Removed

    PS Interfaces

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    Note:

    • optional for Zynq / ZynqMP only

    • add basic PS configuration

    Activated interfaces:

    ...

    anchorTable_PSI
    titlePS Interfaces

      • SREC-File

        *.srec

        Converted Software Application for MicroBlaze Processor Systems




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    File

    File-Extension

    Description

    BIF-File*.bifFile with description to generate Bin-File
    BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
    BIT-File*.bitFPGA (PL Part) Configuration File
    Diverse Reports---Report files in different formats
    Hardware-Platform-Specification-Files*.xsaExported Vivado Hardware Specification for Vitis and PetaLinux
    LabTools Project-File*.lprVivado Labtools Project File
    Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


    Download

    Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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    Reference Design is available on:

    Design Flow

    Page properties
    hiddentrue
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    Notes :

    • Basic Design Steps

    • Add/ Remove project specific description


    Note

    Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

    Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

    See also:

    The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

    TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


    1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
      Image Added
    2. Press 0 and enter to start "Module Selection Guide"
    3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
    4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
      1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
        Note: Select correct one, see TE Board Part Files
         Important: Use Board Part Files, which did not ends with *_tebf0808
    5. Create XAS and export to prebuilt folder
      1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
        Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
    6. Generate Programming Files with Vitis
      1. Run on Vivado TCL: TE::sw_run_vitis -all
        Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
      2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
        Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis

    Launch

    Programming

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    Note:

    • Programming and Startup procedure


    Note

    Check Module and Carrier TRMs for proper HW configuration before you try any design.

    Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

    Get prebuilt boot binaries

    1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
    2. Press 0 and enter to start "Module Selection Guide"
      1. Select assembly version
      2. Validate selection
      3. Select Create and open delivery binary folder
        Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

    QSPI


    1. Connect JTAG and power on carrier with module
    2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
    3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0807
      Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup


    SD

    This does not work, because SD controller is not selected on PS.

    JTAG

    Load configuration and Application with Vitis Debugger into device.

    Usage

    QSPI Boot:

    1. Prepare HW like described on section Programming
    2. Connect UART USB (most cases same as JTAG)
    3. Select QSPI Card as Boot Mode
      Note: See TRM of the Carrier, which is used.
    4. Power On PCB
      Note: 1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from QSPI into OCM, 2. FSBL loads Application into DDR

    System Design - Vivado

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    • Description of Block Design, Constrains... BD Pictures from Export...

    Block Design

    Scroll Title
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    titleBlock Design
    Image Added

    PS Interfaces

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    Note:

    • optional for Zynq / ZynqMP only

    • add basic PS configuration

    Activated interfaces:

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    titlePS Interfaces

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    TypeNote
    DDR
    QSPIMIO
    UART0MIO, please select other one, if you have connected uart to second controller or other MIO
    SWDT0..1
    TTC0..3


    Constrains

    Basic module constrains

    Code Block
    languageruby
    title_i_bitgen.xdc
    set_property BITSTREAM.GENERAL.

    ...

    Constrains

    Basic module constrains

    Code Block
    languageruby
    title_i_bitgen.xdc
    set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

    Design specific constrain

    Not needed.

    Software Design - SDK/HSI

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    • optional chapter separate

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    For SDK project creation, follow instructions from:

    SDK Projects

    Application

    _design]

    Design specific constrain

    Not needed.

    Software Design - SDK/HSI

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    • optional chapter separate

    • sections for different apps

    For SDK project creation, follow instructions from:

    SDK Projects

    Application

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    ----------------------------------------------------------

    FPGA Example

    scu

    MCS Firmware to configure SI5338 and Reset System.

    srec_spi_bootloader

    TE modified 2019.2 SREC

    Bootloader to load app or second bootloader from flash into DDR

    Descriptions:

    • Modified Files: blconfig.h, bootloader.c
    • Changes:
      • Add some console outputs and changed bootloader read address.
      • Add bugfix for 2018.2 qspi flash

    xilisf_v5_11

    TE modified 2019.2 xilisf_v5_11

    • Changed default Flash type to 5.

    ----------------------------------------------------------

    Zynq Example:

    zynq_fsbl

    TE modified 2019.2 FSBL

    General:

    • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

    • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

    • General Changes: 
      • Display FSBL Banner and Device ID

    Module Specific:

    • Add Files: all TE Files start with te_*
      • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
      • CPLD access
      • Read CPLD Firmware and SoC Type
      • Configure Marvell PHY

    zynq_fsbl_flash

    TE modified 2019.2 FSBL

    General:

    • Modified Files: main.c
    • General Changes:
      •  Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation

    ZynqMP Example:

    ----------------------------------------------------------

    zynqmp_fsbl

    TE modified 2019.2 FSBL

    General:

    • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
    • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
    • General Changes: 
      • Display FSBL Banner and Device Name

    Module Specific:

    • Add Files: all TE Files start with te_*
      • Si5338 Configuration
      • ETH+OTG Reset over MIO

    zynqmp_fsbl_flash

    TE modified 2019.2 FSBL

    General:

    • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
    • General Changes:
      •  Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation


    zynqmp_pmufw

    Xilinx default PMU firmware.

    ----------------------------------------------------------

    General Example:

    hello_te0820

    Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

    u-boot

    U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

    Template location: ./sw_lib/sw_apps/

    zynqmp_fsbl

    TE modified 20182019.3 2 FSBL

    General:

    • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
    • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
    • General Changes: 
      • Display FSBL Banner and Device Name

    zynqmp_fsbl_flash

    TE modified 20182019.3 2 FSBL

    General:

    • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
    • General Changes:
      •  Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation

    ...

    DateDocument RevisionAuthorsDescription

    Page info
    modified-date
    modified-date
    dateFormatyyyy-MM-dd

    Page info
    current-version
    current-version
    prefixv.

    Page info
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    modified-user

    • Release 2019.2
    • new assembly variants
    2019-05-22v.10John Hartfiel
    • Release 2018.3
    2019-02-07v.9John Hartfiel
    • new assembly variant

    2018-09-04

    		v.7John Hartfiel
    • Release 2018.2
    2018-02-08v.5John Hartfiel
    • Release 2017.4
    2017-11-14v.3John Hartfiel
    • Release 2017.2
    --all

    Page info
    modified-users
    modified-users

    		--

    ...