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Requirements

This step by step guide covers the tools and console commands for Windows users. The programs and tools this guide uses
are Linux based. Intels approach for making these Linux tools accessible to Windows users is the wrapper Cygwin, because of
that, the steps and console commands in a Linux environment are nearly identical.

All required Editors and tools are part of the Intel FPGA Design software packages.

Only the SD card build requires low level access to the SD card and can therefore only be performed in native Linux environment.

Software:

 - Intel® Quartus® Prime Lite - Version 18.1 build 625

 - Intel® SoC FPGA Embedded Development Suite (SoC EDS) - Version 18.1 build 625 - Extension of Quartus Prime lite

 - Linux Installation - As OS or as a Virtual Machine - Windows Subsystem for Linux is not suitable

Introduction

Introduction

Bringing-up SoC boards can be board dependent. Therefore, an overview introducing into the basic requirements to bring-up the board TEI0022 could be very helpful. To reach this goal, this guide shows users This guide has the objective to give users, with basic knowledge of computers, basic ideas of FPGAs, and Software Design Tools,
a detailed Insight insight into the required steps to build and compile create the necessary files to be able to boot for booting the Hard Processor System
of a (HPS) of an Intel Cyclone V FPGA SoC from a an SD card. The HPS is chosen because it offers a limited amount of complexity and shows the basic
usage of many features from a FPGA Design.

The whole design process is separated along the usage of different programs and or tools. The needs several tools, whereby output files and folders of from one step are
essential for the next processing step. Each step in its own can offer complexity of varying degree on demand. This complexity can not be handled in a simple guide.The usage of programs and tool will be described on point for the indented goal of booting the HPS.

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Step 1 - Intel Quartus Project

 - Setup a project in Quartus Prime Lite (folder: project and project name: HPSexample)

 - Use the Plattform Designer to configure the resources needed to boot the HPS
    (System Memory and SD card access)

Therefore, each step can be handled independently with its complexity if the needed files and folders are available. The usage of tools will be described in sequential order, according to the necessary path, booting the HPS. This process is described by showing the requirements in the next section. The following section displays the necessary steps withing the tool "Intel Quartus Prime Project". After that, the generation of the preloader and the main bootloader from u-boot sources is shown, followed by the generation of the device tree blob. Then, the generation of the kernel and the root filesystem is presented which are needed for the SD card setup for the Intel Cycone V HPS which is delivered afterwards. After that, information regarding the boot process, and additional information are given. Finally, references for further information are mentioned.

Requirements

The requirements for bringing up the HPS in the Intel Cyclone V SoC on the TEI0022 consists of the important settings and tools:

• Correct programmed system controller Intel MAX 10 on board TEI0022
•  Windows:
  • Intel® Quartus® Prime Lite - Version 18.1 build 625
  • Intel® Soc FPGA Embedded Development Suite (Soc EDS) - Version 18.1 build 625
• Linux:
  • git
  • fdisk
  • make
  • mkfs

Intel Quartus Prime project generation

The first step within the HPS booting procedure is using the tool "Intel Quartus Prime". Within this tool it is necessary to create a new project. After that, it is mandatory to configure the resources (system memory and SD card access) withing the Plattform Designer. After that, connect the basis interfaces (UART, I2C - Connect the basic interfaces (Uart and i²c) of the HPS to the board resources  - Compile and compile the project to get the required files and folders for the next steps
    HPSexample.sopinfo / PlattformEditorHPS.qip file and (hps_isw_)handoff folder

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Step 2 - Generation of the preloader and main bootloader from U-Boot sources

Use the handoff folder to generate the preloader and main bootloader

[preloader-mkpimage.bin u-boot.img]

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Step 3 - Generation of the Device Tree Blob

Use the plattformDesigner.sopinfo file to generate the device tree
[dts and dtb]

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Step 4 - SD card setup for Intel Cyclone 5 HPS

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Web sources:

Embedded Linux Beginners Guide
https://rocketboards.org/foswiki/Documentation/EmbeddedLinuxBeginnerSGuide

Introducing the Intel® Quartus® Prime Pro and Standard Edition Software User Guides
https://www.intel.com/content/www/us/en/programmable/products/design-software/fpga-design/quartus-prime/user-guides.html

Intel SoC FPGA Embedded Development Suite User Guide
https://www.intel.com/content/www/us/en/programmable/documentation/lro1402536290550.html

Intel® Soc EDS Support
https://www.intel.de/content/www/de/de/programmable/products/design-software/embedded-software-developers/soc-eds/support.html

Embedded Peripherals IP User Guide
https://www.intel.com/content/www/us/en/programmable/documentation/sfo1400787952932.html

SoC HPS System Generation
https://www.youtube.com/watch?v=8BehnPg8IvM
https://www.youtube.com/watch?v=L8FMSy7Uxjc
https://www.youtube.com/watch?v=vS7pvefsbRM

create the ".sopinfo", the ".qip" files, and the "handoff" folder. Refer to "Intel Quartus Prime project generation" for more detailed information.

Preloader/Bootloader generation

After Intel Quartus Prime project generation, it is necessary to handle System on Chip (SoC) booting. The boot process, according to the next figure, consists of several stages:

• BootROM:

The BootROM is hard coded into the chip. After reset the BootROM code can detect the selected boot source and perform a minimal HPS setup. After that, the preloader can be loaded into the On Chip RAM (OCRM) and can be executed.

• Preloader:

While executing the preloader, a further HPS and SDRAM initialization can be done. After that, the bootloader can be loaded and executed. Bootloader and bare metal applications are supported.

• Bootloader:

The bootloader loads the linux operating system (OS) or a bare metal application into the RAM and starts them. If a linux OS is loaded, the kernel is loaded which loads the linux root file system.

To generate the preloader and the bootloader, the handoff folder, generated in the first stage is used. Refer to "Preloader/Bootloader generation" for more detailed information.

Device Tree Blob generation

In the third stage, the device tree blob is generated with the ".sopfile" file as input from the Plattform Designer in stage one. Refer to "Device Tree Blob Generation" for more detailed information.

Kernel/Root-filesystem generation

In the fourth stage, the generation of the kernel and the root filesystem with a linux system should be shown. Refer to "Kernel/Root-filesystem generation" for more detailed information.

SD card setup

In the fifth stage, the SD card setup is created to prepare the boot medium to bring-up the HPS within Intel Cyclone V HPS. Refer to "SD card setup" for more detailed information.

Boot Process

In this step, further information regarding the boot process are delivered. Refer to "Boot Process" for more detailed information.

Additional Information

In this section, additional descriptive and explanatory information are given. Refer to "Additional Information" for more detailed information.

References

In this reference section, further additionally information are delivered for deeper investigation.

• Building Bootloader
• Embedded Linux Beginners Guide
• Embedded Peripherals IP User Guide
• Device Tree Generation
• Generating and Compiling the Preloader

...

• HPS SoC Boot Guide - Cyclone V SoC Development Kit

...

• Intel® SoC EDS Support
• Intel® SoC FPGA Embedded Development Suite User Guide
• Introducing the Intel® Quartus® Prime Pro and Standard Edition Software User Guides

Generating and Compiling the Preloader
https://rocketboards.org/foswiki/Documentation/AVGSRDPreloader

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• Preloader and U-Boot Customization - v13.1

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• U-Boot programming: A tutorial -- Part I
• U-Boot programming: A tutorial -- Part

...

• II
• U-Boot programming: A tutorial -- Part III

Videos for SoC HPS System Generation

• Preloader and U-boot Generation for Altery Cyclone V SoC
• SoC HPS Quartus II Integration (HW/SW Hand-off)
• SoC HPS System Generation Using Qsys

DTB

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