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The whole design process needs several tools, whereby output files and folders from one step are essential for the next processing step. Therefore, each step can be handled independently with its complexity if the needed files and folders are available. The usage of tools will be described in sequential order, according to the necessary path, booting the HPS. This process is described by showing the requirements in the next section. The following section displays the necessary steps withing the tool "Intel Quartus Prime Project". After that, the generation of the preloader and the main bootloader from u-boot sources is shown, followed by the generation of the device tree blob. Then, the generation of the kernel and the root filesystem is presented which are needed for the SD card setup for the Intel Cycone V HPS which is delivered afterwards. After that, information regarding the boot process, and additional information are given. Finally, references for further information are mentioned.

Requirements

The requirements for bring-bringing up the HPS in the Intel Cyclone V SoC on the TEI0022 consists of the following important settings and tools:

• Correct programmed system controller Intel MAX 10 on board TEI0022
•  WindowsWindows:
  • Intel® Quartus® Prime Lite - Version 18.1 build 625
  • Intel® Soc FPGA Embedded Development Suite (Soc EDS) - Version 18.1 build 625
• Linux:
  • git
  • fdisk
  • make
  • mkfs

Intel Quartus Prime project generation

The first step within the HPS booting procedure is using the tool "Intel Quartus Prime". Within this tool it is necessary to create a new project. After that, it is mandatory to configure the resources (system memory and SD card access) withing the Plattform Designer. After that, connect the basis interfaces (UART, I2C) of the HPS to the board resources and compile the project to create the ".sopinfo", the ".qip" files, and the "handoff" folder. Refer to "Intel Quartus Prime project generation" for more detailed information.

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In the third stage, the device tree blob is generated with the ".sopfile" file as input from the Plattform Designer in stage one. Refer to "Device Tree Blob Generation" for more detailed information.

Kernel/Root-filesystem generation

In the fourth stage, the generation of the kernel and the root filesystem with a linux system should be shown. Refer to "Kernel/Root-filesystem generation" for more detailed information.

SD card setup

In the fourth fifth stage, the SD card setup is created to prepare the boot medium to bring-up the HPS within Intel Cyclone V HPS. Refer to "SD card setup" for more detailed information.

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In this section, additional describtive descriptive and explanatory information are given. Refer to "Additional Information" for more detailed information.

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