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Template Revision 1.8 9 - on construction

Design Name always "TE Series Name" + optional CPLD Name + "CPLD"

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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/SC-CPLD-Firmware


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Table of contents

Table of Contents
outlinetrue

Overview

Firmware for system controller TEI0022 Intel MAX 10 with designator U41: 10M08SAU169C8G

Feature Summary

...

  • Fan Controlcontrol
  • FMC Voltage Control
  • JTAG Controlcontrol
  • LED Controlcontrol
  • UART
  • User Button
  • Power Management
  • button
  • Power management
    • Power regulator mode control
    • FMC Power control
  • Reset management
  • Configuration sheme controlReset Management

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

JTAGSEL0 / JTAGSEL0F9_MAX10JTAGSEL1 / JTAGSEL1E9_MAX10G2_MAX10F6_MAX10G1_MAX10HPS_TDO / HPS_TDOJ6FPGA_TDI / FPGA_TDOJ1M10FTDI_JTAG_TDI/DO / FTDI_TDOF5HPS_TCK / HPS_TCKK1HPS_TDI / HPS_TDIM4HPS_TMS / HPS_TMSM7K2FPGA_TDO / FPGA_TDIL2FPGA_TMS / FPGA_TMSJ2 JTAG TMSFMC_TCK/ FMC_TCKM8FMC_TDI / FMC_TDIM9 JTAG TDIFMC_TMS / TMSM11J5K6K5B4_MAX10L11L13 ResetVID0_SW / VID0_SWVID1_SW / VID1E8D8_MAX10N10CPU_GPIO_1 / CPU_GPIO1N9N11VID0 / VID0B2_MAX10VID1 / VID1C2_MAX10_MAX10PWR_SEL / PWR_SELE4_MAX10USER_BTN_SW / USER_BTN_SWB3D1 UART RXDFPGAGPIO_1 / FPGA_IO1C1_MAX10CPU_GPIO_4 / CPU_GPIO4H4FAN_EN / FAN_END13_MAX10MODE_VCC / MODE_DCDC_VCCD9_MAX10A11_MAX10E10_MAX10F10_MAX10A8B11C112.5 V Power GoodPG_+ / PG_1V8D11B12EN_VCC / EN_VCCA10EN_+2.5V / EN_2V5A12EN_+1.8V / EN_1V8D12+1.8 V Power EnableVCC / LED_VCCF12EN_ / EN_3V3B13EN_+0.9V / EN_0V9F1LED_+1.8 V / LED_1V8H21.8 V Power LedEN_DDR_HPS / EN_DDR_HPSF13_MAX10EN_DDR_FPGA / EN_DDR_FPGAE13_MAX10L1C12_MAX10E1C10Power Enable for Cyclone V VCCPD Voltage3.3V / EN_FMCoutC133 V FMC Power EnableK7POK_FMC / POK_FMCE3PG_VDD_FPGA / Power Good / PG_VDD_HPS Power GoodC9E6D6LED_VDD_DDR_HPS / LED_VDD_DDR_HPSH3G4E5EN_+5.0V / EN_5V0B10B5H1A9B9A6B6BDBUS5 /A4BDBUS4 /A3nSTATUS /C4CONF_DONE /C5BDBUS3 /A2BDBUS6 /A5 /ETH_RST /G5H5M2M1N3N2L3K10K12J12J9H10J13H13H9H8G13L4L5M5N5N4N6
Name / opt. VHD NameDirectionPinBank PowerDescription
BOOTSEL2 / BOOTSEL2outL10+3.3VBoot Select Bit 2HPS boot select pin 2
CONF_DONE_IinL5+3.3VSelect JTAG ConnectionCyclone V CONF_DONE pin
CPU_GPIO_0inN10+3.3VSelect JTAG ConnectionFTDI_JTAG_TC/SK / FTDI_TCKinVoltage selection via software for FMC_VADJ (U43 → VS0 pin)
CPU_GPIO_1inN9+3.3VFTDI JTAG TCKFTDI_JTAG_TDO/DI / FTDI_TDIinVoltage selection via software for FMC_VADJ (U43 → VS1 pin)
CPU_GPIO_2inN11+3.3VFTDI JTAG TDIFTDI_JTAG_TMS/CS / FTDI_TMSinVoltage selection via software for FMC_VADJ (U43 → VS2 pin)
CPU_GPIO_3inL1+3.3VFTDI JTAG TCKFMC power enable control via software
CPU_GPIO_4inH4+3.3VHPS JTAG TDOFan control via software
BDBUS0inD1+3.3VFPGA JTAG TDOFMC_TDO / FMC_TDOin_MAX10FTDI UART TXD pin
BDBUS1outC1+3.3VFMC JTAG TDO_MAX10FTDI UART RXD pin
EN_0V9outF1+3.3V_MAX10

FTDI JTAG TDO

+0.9V power enable
EN_1V8outD12+3.3VHPS JTAG TCK_MAX10+1.8V power enable
EN_2V5outA12+3.3VHPS JTAG TDI_MAX10+2.5V power enable
EN_3V3outB13+3.3VHPS JTAG TMSFPGA_TCK / FPGA_TCKout_MAX10+3.3V HPS JTAG TCKpower enable
EN_5V0outA7+3.3VFPGA JTAG TDI_MAX10+5.0V power enable
EN_DDR_FPGAoutE13+3.3V_MAX10FPGA DDR power enable
EN_DDR_HPSoutF13+3.3VFMC JTAG TCK_MAX10HPS DDR power enable
EN_FMCoutE1+3.3V_MAX10FMC_VADJ power enable
EN_FMC_3V3outC13+3.3V_MAX10FMC JTAG TMSHPS_RST#_SW / HPS_RSTn_SWin+3.3V FMC power enable
EN_FMC_12VoutC12+3.3VReset ButtonHPS_RST#_BO / HPS_RSTn_BOin_MAX10+12.0V FMC power enable
EN_VCCoutA10+3.3VBrown Out DetectionHPS_WARM_RST#_SW / HPS_WARM_RSTn_SWin_MAX10VCC power enable
FAN_ENoutD13+3.3VWarm Reset ButtonFPGA_RST#_SW / FPGA_RSTn_SWin_MAX10Fan control
FMC_PG_C2MoutK7+3.3VFPGA Reset ButtonHPS_RST# / HPS_RSTnoutFMC power good signal to FMC connector
FMC_PRSNT_M2CninJ7+3.3VHPS Reset
HPS_WARM_RST# / HPS_WARM_RSTnoutM3+3.3VHPS Warm Reset
FMC card detection from FMC connector / currently_not_used
FPGA_GPIO_0outK11FPGA_RST# / FPGA_RSTnoutVDD_DDR_FPGAFPGA IO (FPGA pin AG10) / FPGA UART RXD
FPGA_GPIO_1inJ10VDD_DDR_FPGAFPGA IO (FPGA pin AH9) / FPGA UART TXD
FPGA_RSTnoutL13VDD_DDR_FPGAFPGA reset
FPGA_RSTnF8+3.3V_MAX10Power Selection Pin 0 for FMC Voltage_SWinB4+3.3V_MAX10Power Selection Pin 1 for FMC VoltageVID2_SW / VID2_SWinFPGA reset button
FMC_TCKoutM8+3.3VPower Selection Pin 2 for FMC VoltageCPU_GPIO_0 / CPU_GPIO0inFMC JTAG TCK
FMC_TDIoutM9+3.3VCPU GPIO 0 (used for automatic power selection for FMC Voltage)FMC JTAG TDI
FMC_TDOinM10+3.3VCPU GPIO 1 (used for automatic power selection for FMC Voltage)CPU_GPIO_2 / CPU_GPIO2inFMC JTAG TDO
FMC_TMSoutM11+3.3VCPU GPIO 2 (used for automatic power selection for FMC Voltage)FMC JTAG TMS
FPGA_TCKoutK2+3.3VPower Selection Pin 0 for FMC Voltage at U43HPS JTAG TCK
FPGA_TDIoutJ1+3.3VPower Selection Pin 1 for FMC Voltage at U43VID2 / VID2outF4FPGA JTAG TDI
FPGA_TDOinL2+3.3VPower Selection Pin 2 for FMC Voltage at U43FPGA JTAG TDO
FPGA_TMSoutJ2+3.3VPower Selection for Cyclone V FMC VCCPD at U37FPGA JTAG TMS
FTDI_JTAG_TCKinG2+3.3V_MAX10User Button
USER_BTN_FPGA / USER_BTN_FPGAoutG12VDD_DDR_FPGAFPGA User Button
FTDI JTAG TCK
FTDI_JTAG_TDIinF5+3.3V_MAX10

FTDI JTAG TDI

FTDI_JTAG_TDOoutF6BDBUS0 / FTDI_RXDin+3.3V_MAX10FTDI JTAG TDO
FTDI_JTAG_TMSinJ10VDD_DDR_FPGAFPGA IO 1
FPGA_GPIO_0 / FPGA_IO0outK11VDD_DDR_FPGAFPGA IO 0
G1+3.3V_MAX10FTDI JTAG TMS
HPS_TCKoutK1+3.3VHPS JTAG TCK
HPS_TDIoutM4BDBUS1 / FTDI_TXDout+3.3VFTDI UART TXDHPS JTAG TDI
HPS_TDOinJ6+3.3VCPU GPIO 4 (used for fan control)HPS JTAG TDO
HPS_TMSoutM7+3.3VFan ControlHPS JTAG TMS
HPS_RSTnoutL11+3.3VVCC DCDC Mode SelectionMODE / MODE_DCDC_5VoutHPS reset
HPS_RSTn_BOinK6+3.3V+5.0 V DCDC Mode SelectionMODE_DDR_FPGA / MODE_DCDC_FPGAoutBrown Out detection
HPS_RSTn_SWinJ5+3.3VReset button
HPS_WARM_RSTnoutM3+3.3VFPGA DDR Power DCDC Mode SelectionMODE_DDR_HPS / MODE_DCDC_HPSoutHPS warm reset
HPS_WARM_RSTn_SWinK5+3.3VHPS warm reset button
JTAGSEL0 DDR Power DCDC Mode SelectionPG_+5.0V / PG_5V0inF9+3.3V_MAX10+5.0 V Power GoodSelect JTAG connection
JTAGSEL1PG_VCC / PG_VCCinE9+3.3V_MAX10VCC Power GoodPG_+2.5V / PG_2V5inSelect JTAG connection
LED_1V8outH2+3.3V_MAX10+1.8V inpower good led
LED_FMC_VADJoutC9+3.3V_MAX10+1.8 V Power GoodPG_+3.3V / PG_3V3inFMC_VADJ power good led
LED_VCCoutF12+3.3V_MAX10+3.3 V Power GoodVCC power good led
LED_VDD_DDR_FPGAoutE6+3.3V_MAX10VCC Power EnableFPGA DDR VDD power good led
LED_VDD_DDR_HPSoutH3+3.3V_MAX10+2.5 V Power EnableHPS DDR VDD power good led
LED_VTT_DDR_FPGAoutD6+3.3V_MAX10FPGA DDR VTT power good led
LED_VTT_DDR_HPSoutG4+3.3V_MAX10VCC Power LedHPS DDR VTT power good led
MODEoutA11+3.3V_MAX10+5.0V voltage regulator mode selection
MODE_DDR_FPGAoutE10+3.3V_MAX10+3.3 V Power EnableVoltage regulator mode selection for FPGA DDR power 
MODE_DDR_HPSoutF10+3.3V_MAX10+0.9 V Power EnableVoltage regulator mode selection for HPS DDR power
MODE_VCCoutD9+3.3V_MAX10VCC voltage regulator mode selection
MSEL0outN5+3.3VConfiguration mode selection pin 0
MSEL1outN3+3.3VHPS DDR Power EnableConfiguration mode selection pin 1
MSEL2outN2+3.3VFPGA DDR Power EnableCPU_GPIO_3 / CPU_GPIO3inConfiguration mode selection pin 2
MSEL3outN4+3.3VCPU GPIO 3 (used for FMC Power Enable)Configuration mode selection pin 3
MSEL4outN6FMC_PRSNT_M2C# / FMC_PRSNT_M2CninJ7+3.3VFMC Card Detection from FMC ConnectorEN_FMC_+12.0V / EN_FMC_12VoutConfiguration mode selection pin 4
nSTATUS_IinL4+3.3V+12.0 V FMC Power EnableEN_FMC / EN_FMCoutCyclone V nSTATUS pin
PG_1V8inD11+3.3V_MAX10Power Enable for FMC Voltage at U43PWR_SWT_EN / PWR_VCCPD_ENout+1.8V power good signal
PG_2V5inC11+3.3V_MAX10EN_FMC_+2.5V power good signal
PG_3V3inB12+3.3V_MAX10+3.FMC_PG_C2M / FMC_PG_C2Mout3V power good signal
PG_5V0inA8+3.3VFMC Power Good Signal to FMC Connector_MAX10+5.0V power good signal
PG_VCCinB11+3.3V_MAX10Power Good for FMC Voltage at U43VCC power good signal
PG_VDD_FPGAinE12+3.3V_MAX10FPGA VDD DDR power good signal
PG_VDD_HPSinG10+3.3V_MAX10HPS VDD DDR LED_FMC_VADJ / LED_FMC_VADJoutpower good signal
PG_VTT_FPGAinB10+3.3V_MAX10Power Good Led for FMC Voltage at U43LED_VDD_DDR_FPGA / LED_VDD_DDR_FPGAoutFPGA VTT DDR power good signal
PG_VTT_HPSinB5+3.3V_MAX10FPGA DDR VDD Power Good LedLED_VTT_DDR_FPGA / LED_VTT_DDR_FPGAoutHPS VTT DDR power good signal
POK_FMCinE3+3.3V_MAX10FPGA DDR VTT Power Good LedFMC_VADJ power good signal
PWR_SELoutE4+3.3V_MAX10HPS DDR VDD Power Good LedLED_VTT_DDR_HPS / LED_VTT_DDR_HPSout

Power selection pin for FMC_VCCPD voltage at U37 (Cyclone V - Bank 8A VCCPD voltage)

PWR_SWT_ENoutC10+3.3V_MAX10HPS DDR VTT Power Good LedJTAGEN /in

Power enable pin for FMC_VCCPD voltage at U37

STATUSoutH1+3.3V_MAX10Select JTAG Connectionstatus led
USER_BTN_FPGAoutA7+3.3V_MAX10+5.0 V Power EnablePG_VTT_FPGA / PG_VTT_FPGAinG12VDD_DDR_FPGAFPGA user button pin
USER_BTN_HPSoutM2+3.3VHPS user button pin
USER_BTN_SWinB3+3.3V_MAX10FPGA VTT DDR Power GoodPG_VTT_HPS / PG_VTT_HPSin/outuser button
VID0_SWinF8+3.3V_MAX10HPS VTT DDR Power GoodSTATUS /-Dip switch S8A for FMC_VADJ voltage selection
VID1_SWinE8+3.3V_MAX10/ currently_not_usedBDBUS2 /-B1Dip switch S8B for FMC_VADJ voltage selection
VID2_SWinD8+3.3V_MAX10/ currently_not_usedBCBUS2 /-Dip switch S8C for FMC_VADJ voltage selection
VID0outB2+3.3V_MAX10/ currently_not_usedDEVCLRn /-Voltage selection pin 0 (VS0) for FMC_VADJ voltage at U43
VID1outC2+3.3V_MAX10/ currently_not_usedBDBUS7 /-Voltage selection pin 1 (VS1) for FMC_VADJ voltage at U43
VID2outF4+3.3V_MAX10/ currently_not_usedBCBUS1 /-Voltage selection pin 2 (VS2) for FMC_VADJ voltage at U43
JTAGENinE5+3.3V_MAX10/ currently_not_usedenable/disable JTAG access to system controller MAX10
BDBUS2-B1+3.3V_MAX10/ currently_not_used
BDBUS3-A2+3.3V_MAX10/ currently_not_used
BDBUS4-A3+3.3V_MAX10/ currently_not_used
BDBUS5-A4+3.3V_MAX10/ currently_not_used
BDBUS6-A5+3.3V_MAX10/ currently_not_used
BDBUS7-A6+3.3V_MAX10/ currently_not_used
CLK_MAX10-H6+3.3VSI5338A → CLK2A pin / currently_not_used
CLKSEL0-N8+3.3VCyclone V clock select pin 0 / currently_not_used
USB_RSTCLKSEL1-N7+3.3VCyclone V clock select pin 1 / currently_not_usedUSER
_BTN_HPS /DEVCLRn-B9+3.3V_MAX10Device-wide reset for MAX 10 / currently_not_used
nCONFIGETH_I /RST-G5+3.3VEthernet phy reset / currently_not_usedMSEL1 /
FMC_SCL-N12+3.3VFMC I²C interface / currently_not_usedMSEL2 /
FMC_SDA-M13+3.3VFMC I²C interface / currently_not_usedUSB_
HUB_RST /FMC_TRST#-M12+3.3VFMC JTAG test reset / currently_not_used
FPGA_GPIO_9 /2-K12VDD_DDR_FPGAFPGA IO (FPGA pin AF11) / currently_not_used
FPGA_GPIO_3 /-L12VDD_DDR_FPGAFPGA IO (FPGA pin AG11) / currently_not_used
FPGA_GPIO_2 /4-G13VDD_DDR_FPGAFPGA IO (FPGA pin AA13) / currently_not_used
FPGA_GPIO_11 /5-H13VDD_DDR_FPGAFPGA IO (FPGA pin AB13) / currently_not_used
FPGA_GPIO_8 /6-H8VDD_DDR_FPGAFPGA IO (FPGA pin AK2) / currently_not_used
FPGA_GPIO_12 /7-H9VDD_DDR_FPGAFPGA IO (FPGA pin AK3) / currently_not_used
FPGA_GPIO_10 /8-J9VDD_DDR_FPGAFPGA IO (FPGA pin AJ4) / currently_not_used
FPGA_GPIO_5 /9-K10VDD_DDR_FPGAFPGA IO (FPGA pin AK4) / currently_not_used
FPGA_GPIO_7 /10-J13VDD_DDR_FPGAFPGA IO (FPGA pin AE13) / currently_not_used
FPGA_GPIO_6 /11-J12VDD_DDR_FPGAFPGA IO (FPGA pin AF13) / currently_not_used
FPGA_GPIO_4 /12-H10VDD_DDR_FPGAFPGA IO (FPGA pin AD14) / currently_not_used
nSTATUSHPS_SPI_I SS/BOOTSEL0-K8+3.3VHPS boot select pin 0 / currently_not_used
CONF_DONE_I /HPS_TRST#-M5+3.3VHPS JTAG test reset / currently_not_used
HPSnCONFIG_TRST# /I-M1+3.3VCyclone V nCONFIG pin / currently_not_used
MSEL0 QSPI_CS/BOOTSEL1-J8+3.3VHPS boot select pin 1 / currently_not_usedMSEL3 /
USB_HUB_RST-L3+3.3VUSB hub (U33) reset / currently_not_usedMSEL4 /
USB_RST-H5+3.3V/ currently_not_usedCLKSEL0 /-N8+3.3VUSB phy (U8) reset / currently_not_used
CLKSEL1 /-N7+3.3V/ currently_not_used
FMC_TRST# /-M12+3.3V/ currently_not_used
FMC_SDA /-M13+3.3V/ currently_not_used
HPS_SPI_SS/BOOTSEL0-K8+3.3V/ currently_not_used
QSPI_CS/BOOTSEL1-J8+3.3V/ currently_not_used
FMC_SCL /-N12+3.3V/ currently_not_used

Functional Description

DCDC Mode Control

The mode signals are connected to "1".

...

MODE_DCDC_VCC,

MODE_DCDC_5V

...

1

...

MODE_DCDC_FPGA,

MODE_DCDC_HPS

...

Functional Description

Fan control

Can be enabled/disabled through the Intel Cyclone V HPS "CPU_GPIO_4" pin.

JTAG control

The FTDI JTAG is connected to the Intel MAX 10, the Intel Cyclone V HPS and Fabric and to the FMC Connector according to the following table.

JTAGSEL0JTAGSEL1JTAGENJTAG selection
XX1 - (ON)Intel MAX 10
0 - (ON)0 - (ON)0 - (OFF)Cyclone V HPS
0 - (ON)1 - (OFF)0 - (OFF)Cyclone V FPGA
1 - (OFF)0 - (ON)0 - (OFF)FMC

LED Control

LedDescription
LED_1V8connected to PG_1V8
LED_FMC_VADJconnected to POK_FMC
LED_VCCconnected to PG_VCC
LED_VDD_DDR_FPGAconnected to PG_VDD_FPGA
LED_VDD_DDR_HPSconnected to PG_VDD_HPS
LED_VTT_DDR_FPGAconnected to PG_VTT_FPGA
LED_VTT_DDR_HPSconnected to PG_VTT_HPS
STATUS

Status LED (D25). Status depends on blink sequence and priority.

  1. LED OFF : no faults
  2. *ooooooo : CONF_DONE_I is low-> Cyclone V SoC not programmed
  3. **oooooo : not used
  4. ***ooooo : nSTATUS_I failed
  5. ****oooo : pressed FPGA_RSTn_SW button
  6. *****ooo : pressed HPS_RSTn_SW / HPS_WARM_RSTn_SW button
  7. ******** : brown out detection (U54) - HPS_RSTn_BO is low
  8. LED ON : not used

UART

UART signal are routed directly from FTDI chip through Intel MAX 10 to Cyclone V FPGA.

FTDI FT2232H-56QDirectionCyclone V FPGA
BDBUS0 (TXD)→FPGA_GPIO_0 (RXD, Pin AG10)
BDBUS1 (RXD)←FPGA_GPIO_1 (TXD, Pin AH9)

User button

The user button is connected to the USER_BTN_FPGA pin AB21 and USER_BTN_HPS pin A23 on the Cyclone V FPGA.

Power management

The power sequencing is handled inside the system controller according to the next figure, starting with DCDC U46 +5.0V.


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Fan Control

Can be enabled/disabled through the Intel Cyclone V HPS "CPU_GPIO4".

FMC Voltage Control

The power is enabled if signal "CPU_GPIO3" is set to "1" and there is an FMC card. Then, the +12.0 V level is enabled. After that, the adjustable voltage is enabled. Finally, the +3.3 V level is enabled. Then, the signal "FMC_PG_C2M" is asserted.

JTAG Control

The FTDI JTAG is connected to the Intel MAX10, the Intel Cyclone V HPS and Fabric and to the FMC Connector according to the following table.

...

LED Control

The leds signals their power good status.

UART

The second channel of the JTAG FTDI interface delievers an UART connection to the Intel Cyclone V fabric.

User Button

The User Button is connected to the FPGA.

Power Management

The power sequencing is handled inside the system controller according to the next figure.

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The FMC power sequencing depends on the assertion through the signals "CPU_GPIO3" and "FMC_PRSNT_M2Cn". If both of them are asserted, the +12.0 V level starts, followed by the adjustabel voltage level with the according pre-driver voltage and finally, the +3.3 V level is started.

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Voltage regulator mode control

DesignatorSignalStateDescription
U45

MODE_VCC

1

Forced continous mode
U46MODE1Forced continous mode
U56

MODE_DDR_FPGA

1Pulse-skipping mode for VDD
U50MODE_DDR_HPS1Pulse-skipping mode for VDD

For more information about possible modes see datasheet of voltage regulators.

FMC power control

The FMC adjustable voltage selection FMC_VADJ (U43) can be done by the dip switches VID0_SW (S8A), VID1_SW (S8B) and VID2_SW (S8C) or by the Intel Cyclone V HPS via CPU_GPIO_0 pin, CPU_GPIO_1 pin and CPU_GPIO_2 pin. The choice is done according to the next table.

VID2_SW (S8C)/

CPU_GPIO_2

VID1_SW (S8B)/

CPU_GPIO_1

VID0_SW (S8A)/

CPU_GPIO_0

VoltageNotes
ON / 0ON / 0ON / 03.3V-
ON / 0ON / 0OFF / 12.5V-
ON / 0OFF / 1ON / 01.8V-
ON / 0OFF / 1OFF / 11.5V-
OFF / 1ON / 0ON / 01.25V-
OFF / 1ON / 0OFF / 11.2V-
OFF / 1OFF / 1ON / 00.8Vnot supported by Intel Cyclone V
OFFOFFOFFCPU-dependentselect voltages with CPU_GPIO_0/CPU_GPIO_1/CPU_GPIO_2  pins

The FMC power can be enabled or disabled via software with CPU_GPIO_3 pin, when the dip switches VID0_SW (S8A), VID1_SW (S8B) and VID2_SW (S8C) are set to OFF. If the FMC_VADJ voltage is selected by the dip switches, FMC power is always enabled.

The FMC power sequencing is handled as shown in the next figure.


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The FMC adjustable voltage selection can be done manually by the switches or automatically by the Intel Cyclone V HPS. The choice is done via the switches according to the next table. The voltage for the Intel Cyclone V HPS pre-driver is selected according to the voltage setting.

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Reset Management

The reset buttons are connected via the system controller to the according reset locations.

DesignatorNameconnected toNotes
S1HPS_RSTn_SWHPS_RSTnButton
U54HPS_RSTn_BOHPS_RSTnBrown out detection
S3HPS_WARM_RSTn_SWHPS_WARM_RSTnButton
S4FPGA_RSTn_SWFPGA_RSTnButton

Configuration sheme control

MSEL4MSEL3MSEL2MSEL1MSEL0Configuration sheme
00010FPP x16 Fast, compression feature enabled

Appx. A: Change History and Legal Notices

Revision Changes

SC REV03 to REV04

  • PCB REV03 support only
  • bugfixes
  • add status led control
  • add USER_BTN_HPS, CONF_DONE_I, nSTATUS_I pins

SC REV02 to REV03

  • bugfixes
  • add configuration sheme

SC

Reset Management

The reset buttons are connected via the system controller to the according reset locations. That means that, if the reset button S1 or the brown-out detection is asserted, the Cyclone V should be reseted. If the warm reset button S3 is asserted, the Cyclone V should be warm reseted. If the FPGA reset button S4 is asserted, the FPGA could be reseted.

Appx. A: Change History and Legal Notices

Revision Changes

CPLD REV01 to REV02

  • Changed pin connections
  • Changed JTAG connection
  • Changed reset connection
  • Changed FMC Vadj Voltage selection
  • Changed power sequencing

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

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REV04REV03

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Work in progress


Revision 04 release
2020-06-03v.9REV03REV02Thomas DückRevision 03 release
2020-02-19v.197REV02REV02

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Initial release

All

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Legal Notices

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IN:Legal Notices
IN:Legal Notices

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