Page History
...
The mode signals are connected to "1".
| Signal | State | Description |
|---|---|---|
MODE_DCDC_VCC, MODE_DCDC_5V | 1 | Forced Continous Mode |
| 0 | Discontinous Mode | |
MODE_DCDC_FPGA, MODE_DCDC_HPS | 1 | Pulse-Skipping Mode for VDD |
| 0 | Forced Continous Mode for VDD |
Fan Control
Can be enabled/disabled through the Intel Cyclone V HPS "CPU_GPIO4".
...
The FTDI JTAG is connected to the Intel MAX10, the Intel Cyclone V HPS and Fabric and to the FMC Connector according to the following table.
| JTAG_SEL0 | JTAG_SEL1 | JTAGEN | JTAG Connection |
|---|---|---|---|
| X | X | 1 - (ON) | Intel MAX10 |
| 0 - (ON) | 0 - (ON) | 0 - (OFF) | Cyclone V HPS |
| 0 - (ON) | 1 - (OFF) | 0 - (OFF) | Cyclone V FPGA |
| 1 - (OFF) | 0 - (ON) | 0 - (OFF) | FMC |
LED Control
The leds signals their power good status.
...
The FMC adjustable voltage selection can be done manually by the switches or automatically by the Intel Cyclone V HPS. The choice is done via the switches according to the next table. The voltage for the Intel Cyclone V HPS pre-driver is selected according to the voltage setting.
| S8-C | S8-B | S8-A | Voltage | Setting |
|---|---|---|---|---|
| ON | ON | ON | 3.3 V | Manual |
| ON | ON | OFF | 2.5 V | Manual |
| ON | OFF | ON | 1.8 V | Manual |
| ON | OFF | OFF | 1.5 V | Manual |
| OFF | ON | ON | 1.25 V | Manual |
| OFF | ON | OFF | 1.2 V | Manual |
| OFF | OFF | ON | 0.8 V | Manual |
| OFF | OFF | OFF | CPU-dependent | CPU |
Reset Management
The reset buttons are connected via the system controller to the according reset locations. That means that, if the reset button S1 or the brown-out detection is asserted, the Cyclone V should be reseted. If the warm reset button S3 is asserted, the Cyclone V should be warm reseted. If the FPGA reset button S4 is asserted, the FPGA could be reseted.
...
Overview
Content Tools