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Bringing-up SoC boards can be board dependent. Therefore, an overview introducing into the basic requirements to bring-up the board TEI0022 could be very helpful. To reach this goal, this guide shows users with basic knowledge of computers, basic ideas of FPGAs, and Software Design Tools, a detailed insight into the required steps to create the necessary files for booting the Hard Processor System (HPS) of an Intel Cyclone V SoC from an SD card.

The whole design process needs several tools, whereby output files and folders from one step are essential for the next processing step. Therefore, each step can be handled independently with its complexity if the needed files and folders are available. The usage of tools will be described in sequential order, according to the necessary path, booting the HPS. This process is described by showing the requirements in the next section. The following section displays the necessary steps withing the tool "Intel Quartus Prime Project". After that, the generation of the preloader and the main bootloader from u-boot sources is shown, followed by the generation of the device tree blob. Then, the SD card setup for the Intel Cycone V HPS is delivered and finally. After that, information regarding the boot process, and additional information are given. Finally, references for further information are mentioned.

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• Windows:
  • Intel® Quartus® Prime Lite - Version 18.1 build 625
  • Intel® Soc FPGA Embedded Development Suite (Soc EDS) - Version 18.1 build 625
• Linux:
  • fdisk
  • mkfs

Intel Quartus

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Prime project generation

The first step within the HPS booting procedure is using the tool "Intel Quartus Prime". Within this tool it is necessary to create a new project. After that, it is mandatory to configure the resources (system memory and SD card access) withing the Plattform Designer. After that, connect the basis interfaces (UART, I2C) of the HPS to the board resources and compile the project to create the ".sopinfo", the ".qip" files, and the "handoff" folder. Refer to "Intel Quartus Prime project generation" for more detailed information.

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The BootROM is hard coded into the chip. After reset the BootROM code can detect the selected boot source and perform a minimal HPS setup. After that, the preloader can be loaded into the On Chip RAM (OCRM) and can be executed.

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To generate the preloader and the bootloader, the handoff folder, generated in the first step stage is used. Refer to "Preloader/Bootloader generation" for more detailed information.

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Device Tree Blob generation

In the third stepstage, the device tree blob is generated with the ".sopfile" file as input from the Plattform Designer in step 1stage one. Refer to "Device Tree Blob Generation" for more detailed information.

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In the final step, the SD card setup is created to prepare the boot medium to bring-up the HPS within Intel Cyclone V HPS. Refer to "SD card setup" for more detailed information.

Boot Process

Additional Information

References

In this reference section, further additionally information are delivered for deeper investigation.

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