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The Trenz Electronic TE0022-01 board 02 is a SoC module board based on Intel Cyclone V FPGA, an ethernet PHY, one GByte DDR3 SDRAM per HPS and FPGA and one 32 MByte Quad SPI Flash memory for configuration and operation per HPS and FPGA, and powerful switching-mode power supplies for all on-board voltages.

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Scroll Title
anchorFigure_OV_BD
titleTEI0022 -01 block diagram


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Main Components

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titleTEI0022 main components


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  1. Intel Cyclone V, U10
  2. DDR3 SDRAM, U26...27
  3. DDR3 SDRAM, U28...29
  4. FMC, J4
  5. PMOD, P1...4
  6. SD Card Connector, J3
  7. Ethernet PHY, U1
  8. RJ45 Connector, J1
  9. USB ULPIPHY, U8
  10. USB HUB, U33
  11. USB Connector, J2, J12
  12. HDMI Transmitter, U23
  13. HDMI Connector, J11
  14. Intel MAX10, U41
  15. Micro USB to UART Interface, J5, U30
  16. USB to JTAG , U21
  17. Micro USB JTAG and UART, J13
  18. SMA Connector
  19. Push Button, S1, S3...5
  20. LED
  21. 4-Bit DIP Switch, S2, S7...8
  22. 12 V Power Jack, J6
  23. Clock Generator, U48
  24. Programmable Clock Generator, U3
  25. QSPI - FPGA PS, U6
  26. QSPI - FPGA PL, U15
  27. Temperature Sensor, U16
  28. EEPROM, U38

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The FMC connector provides further interfaces like JTAG and I²C interfaces:

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titleFMC connector pin-outs of available interfaces

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InterfaceI/O Signal CountPin schematic Names / FMC PinsConnected toNotes
JTAG5

FMC_TCK, Pin J4-D29

FMC_TMS, Pin J4-D33

FMC_TDI, Pin J4-D30

FMC_TDO, Pin J4-D31

FMC_TRST#, Pin J4-D34

Intel MAX10 U41, Bank 3VCCIO: +3.3V
I2C2

FMC_SCL, Pin J4-C30

FMC_SDA, Pin J4-C31

Intel MAX10 U41, Bank 3 and Intel Cyclone V U10, Bank 7AI2C-lines pulled-up to +3.3V
Control Lines2

FMC_PRSNT_M2C#, Pin J4-H2 (pulled-up to +3.3V)

FMC_PG_C2M, Pin J4-D1 (pulled-up to +3.3V)

Intel MAX10 U41, Bank 3 and Intel Cyclone V U10, Bank 5B / 7C

'PG' = 'Power Good'-signal

'C2M' = carrier to (Mezzanine) module

'M2C' = (Mezzanine) module to carrier


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titleAvailable VCCIO voltages on FMC connector

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VCCIO Schematic NameFMC Connector J4 PinsNotes
+12.0V_FMCC35/C37extern 12V 12 V power supply
+3.3V_FMCD36/D38/D40/C393.3V 3 V peripheral supply voltage
+3.3VD323.3V 3 V peripheral supply voltage
FMC_VADJH40/G39adjustable FMC VCCIO voltage, supplied by DC-DC converter U43
FMC_VREF_A_M2CH1adjustable reference voltage


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titleSMA connectors

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SMA Connector

Signal Schematic Names

Connected to

Notes
J7SMA_CLK_OUT_pClock Generator U3, Pin 22Assembly option
J10SMA_CLK_OUT_nClock Generator U3, Pin 21Assembly option
J8TRIGGER_OUTPUTIntel Cyclone V U10, Pin AE29
J9TRIGGER_INPUTIntel Cyclone V U10, Pin AA26

J15

EXT_CLK_INPUTIntel Cyclone V U10, Pin Y26
J17CLK_INPUTIntel Cyclone V U10, Pin AA26AD29
J18SMA_CLK_INClock Generator U3, Pin 1

Assembly option


FAN Connector

The TEI0022 board offers one a FAN connector for cooling the FPGA device. Depending on the assembly 5 V or 12 V are usable.

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titleFAN connectors

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Connector

Signal Schematic Names

Connected to

Notes
2-Pin FAN Connector J16, 5 V or 12 V power supply depending on R270/271 with BTS4141N High Side Switch U55

FAN_EN,

(High Side Switch U55, Pin 3)

Intel MAX10 U41, Pin C1D13Intel Cyclone V cooling FAN


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According to the JTAGEN and JTAGSEL[1..0] pins the management controller Intel MAX10 (U41), the Intel Cyclone V HPS (U10), the Intel Cyclone V FPGA (U10) or the FMC (J4) can be accessed via the micro USB B connector J13.

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titleTEI0022 -01 JTAG


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Micro USB Connector (UART)
Anchor
UART
UART

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The TEI0022 provides an HDMI Connector J11.

SD Card Connector

SD Card connector J3 is connected to the Intel Cyclone V U10.

RJ45 Connector

The board TEI0022 provides an ethernet interface via the RJ45 connector J1.

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The TEI0022 provides three independent I2C busses. One bus is used to connect the FMC I2C with the Intel Cyclone V HPS. The second bus is used to connect the HDMI device to the Intel Cyclone V FPGA. The third bus is used to handle the other on-board I2C devices. Via assembly option, it is possible to connect bus two to bus three.

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titleOn-board peripherals' I2C-interfaces device slave addresses

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BusI2C DeviceDesignatorI2C AddressSchematic Names of I2C Bus LinesNotes
HPS I2CTemperature SensorU160x4AU16HPS_I2C_SCL / HPS_I2C_SDA3.3 V reference voltage
HPS I2CProgrammable Clock GeneratorU30x70U3HPS_I2C_SCL / HPS_I2C_SDA3.3 V reference voltage
HPS I2CEEPROMU380x50U38HPS_I2C_SCL / HPS_I2C_SDA3.3 V reference voltage
HDMI I2CHDMIU230x72U23HPSHDMI_I2C_SCL / HPS _I2C_SDA3.3 V reference voltage
HPS FMC I2CFMCJ40x50J4FMC_SCL / FMC_SDA3.3 V reference voltage


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titleTEI0022 -01 I2C


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On-board Peripherals

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Chip/InterfaceDesignatorNotes
System Controller Intel MAX10U41
Intel Cyclone VU10
DDR3 SDRAMU26...29
Gigabit Ethernet PHYU1
High-Speed USB ULPI PHYU8
4-Port USB 2.0 HubU33
HDMI TransmitterU23
FTDI (JTAG)U21
FTDI (UART)U30
DIP-SwitchesS2, S7...8
ButtonsS1, S3...5


On-Board LEDsD1...15, D17...23, D25
Temperature SensorU16
QSPIU6, U15
EEPROMU31, U38
Clock SourcesOscillatorU48, U32, U34, U48
Programmable Clock GeneratorU3
Power MonitoringU54


System Controller Intel MAX10MAX 10

The TEI0022 is equipped with an Intel MAX10 MAX 10 (U41) which is the central system management unit where essential control signals are logically linked by the implemented logic of the FPGA firmware. This generates output signals to control the system, the on-board peripherals and the interfaces. Interfaces like JTAG and buttons between the on-board peripherals and to the FPGA-module are by-passed, forwarded and controlled by the System Controller. Other tasks of the System Controller are the monitoring of the power-on sequence and configuration of the Intel Cyclone V FPGA. The functionalities and configuration of the pins depend on its firmware.

Intel Cyclone V

The on TEI0022 board used Intel Cyclone V device used at the TEI0022 board is a SoC with integrated ARM-based HPS. The 5CSEMA5F31C8N version delivers one hard memory controller, 80K logic elements in an FineLineBGA (FBGA) with 896 pins for the commercial temperature range of TJ = 0...85 °C with speed grade eight.

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Scroll Title
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titleEthernet PHY to HPS connections

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BankSignal NameSignal Description
7BETH_TXCKRGMII Transmit Reference Clock
7BETH_TXD0RGMII Transmit Data 0
7BETH_TXD1RGMII Transmit Data 1
7BETH_TXD2RGMII Transmit Data 2
7BETH_TXD3RGMII Transmit Data 3
7B

ETH_TXCTL

RGMII Transmit Control
7BETH_RXCKRGMII Receive Reference Clock
7BETH_RXD0RGMII Receive Data 0
7BETH_RXD1RGMII Receive Data 21
7BETH_RXD2RGMII Receive Data 32
7BETH_RXD3RGMII Receive Data 43
7B

ETH_RXCTL

RGMII Receive Control
7CETH_RSTReset
7BETH_MDCManagement Data Clock
7BETH_MDIOManagement Data I/O
7BPHY_INTInterrupt


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titleUSB PHY interface connections

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PHY PinConnected toNotes
ULPIIntel Cyclone V HPS (U10)
REFCLK24 MHz from on board oscillator (U34)
REFSEL[0..2]High (3.3 V)
RESETBIntel Cyclone V HPS (U10) and Intel MAX 10 (U41)
DP, DM4-port USB 2.0 Hub (U33)
CPENNot Connected.
VBUSPull-up to 5 V.
IDNot Connected.


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titleDIP-switch S7 functionality description

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DIP-switch S7Position ONPosition OFFNotes
S7-1HPS_SPI_SS/BOOTSEL0 is lowHPS_SPI_SS/BOOTSEL0 is highBoot select (Firnware Firmware dependent)
S7-2QSPI_CS/BOOTSEL1 is lowQSPI_CS/BOOTSEL1 is highBoot select (Firnware Firmware dependent)
S7-3JTAGSEL0 is lowJTAGSEL0 is highJTAG select (Firnware Firmware dependent)
S7-4JTAGSEL1 is lowJTAGSEL1 is highJTAG select (Firnware Firmware dependent)


DIP-Switch S8

The table below describes the functionalities of the switches of DIP-switch S8 at their single positions:

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titleDIP-switch S8 functionality description

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DIP-switch S8Position ONPosition OFFNotes
S8-1JTAGEN is highJTAGEN is lowJTAG selectS8-2VID0_SW is lowVID0_SW is highFMC_VADJ selection (Firnware dependent)
S8-32VID1_SW is lowVID1_SW is highFMC_VADJ selection (Firnware dependent)
S8-43VID2_SW is lowVID2_SW is highFMC_VADJ selection (Firnware dependent)
S8-4JTAGEN is highJTAGEN is lowJTAG select


Buttons

There are four buttons present on the TEI0022 board. The following section describes the functionalities of the particular buttons. The final functionality is set by the management Intel MAX10.

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titleButtons functionality description

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ButtonPosition ONPosition OFFNotes
S1HPS_RST#_SW is highlowHPS_RST#_SW is lowhighReset (cold) the Intel Cyclone V HPS (Firnware Firmware dependent)
S3HPS_WARM_RST#_SW is highlowHPS_WARM_RST#_SW is lowhighReset (warm) the Intel Cyclone V HPS (Firnware Firmware dependent)
S4FPGA_RST#_SW is highlowFPGA_RST#_SW is lowhighReset the Intel Cyclone V FPGA (Firnware Firmware dependent)
S5USER_BTN_SW is highlowUSER_BTN_SW is lowhighUser button (Firnware Firmware dependent)


On-Board LEDs

The TEI0022 board is equipped with several LEDs to signal current states and activities. The functionality of the LEDs D11...14 are user LEDs. The LED D8 shows the Intel Cyclone V configuration progress. LEDs D15, D18...19 shows the UART connection and the other LEDs mentioned in the table are supply power status LEDs.

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titleOn-board LEDs

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DesignatorColorConnected toActive LevelNote
D11GreenIntel Cyclone V HPSLHUser LED
D12GreenIntel Cyclone V HPSLHUser LED
D13GreenIntel Cyclone V FPGALHUser LED
D14GreenIntel Cyclone V FPGALHUser LED
D8GreenIntel Cyclone V FPGA, Intel MAX 10LStatus: Configuration "Done"
D15GreenFT234XDLUART
D18GreenUART TXHLUART
D19GreenUART RXHLUART
D21Green+12.0VHStatus of +12.0V voltage rail
D1Green+12.0V_FMCHStatus of +12.0V_FMC voltage rail
D2Green+5.0VHStatus of +5.0V voltage rail
D3Green+3.3VHStatus of +3.3V voltage rail
D20Green+3.3V_MAX10HStatus of +3.3V_MAX10 voltage rail
D22Green+3.3V_FMCHStatus of +3.3V_FMC voltage rail
D4Green+2.5VHStatus of +2.5V voltage rail
D5Green+1.8VIntel MAX 10HStatus of +1.8V voltage rail
D7GreenVCCIntel MAX 10HStatus of VCC voltage rail
D9GreenFMC_VADJIntel MAX 10HStatus of FMC_VADJ voltage rail
D6GreenVDD_DDR_FPGAIntel MAX 10HStatus of VDD_DDR_FPGA voltage rail
D23GreenVDD_DDR_HPSIntel MAX 10HStatus of VDD_DDR_HPS voltage rail
D17GreenVTT_DDR_FPGAIntel MAX 10HStatus of VTT_DDR_FPGA voltage rail
D10GreenVTT_DDR_HPSIntel MAX 10HStatus of VTT_DDR_HPS voltage rail
D25GreenRedIntel Cyclone V HPS U10, Pin B23LMAX 10HStatusStatus of the daughterboard identification


Temperatur Sensor

The temperature sensor ADT7410 (U16) is implemented on the TEI0022 board.

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titleHPS Quad SPI interface signals and connections

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Signal NameQSPI Flash Memory U6 PinFPGA Pin
QSPI_CS/BOOTSEL1S#, Pin C2Bank 7B, Pin A18
QSPI_CLKC, Pin B2Bank 7B, Pin D19
QSPI_DATA0DQ0, Pin D3Bank 7B, Pin C20
QSPI_DATA1DQ1, Pin D2Bank 7B, Pin H18
QSPI_DATA2DQ2, Pin C4Bank 7B, Pin A19
QSPI_DATA3DQ3, Pin D4Bank 7B, Pin E19QSPI_RSTRST#, Pin A4Bank 7A, Pin E24



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titleFPGA Quad SPI interface signals and connections

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Signal NameQSPI Flash Memory U15 PinFPGA Pin
nCSOS#, Pin C2Bank 3A, Pin AB8
AS_DCKC, Pin B2Bank 3A, Pin U7
AS_DATA0DQ0, Pin D3Bank 3A, Pin AE6
AS_DATA1DQ1, Pin D2Bank 3A, Pin AE5
AS_DATA2DQ2, Pin C4Bank 3A, Pin AE8
AS_DATA3DQ3, Pin D4Bank 3A, Pin AC7
AS_RSTRST#, Pin A4Bank 7A, Pin B22


EEPROMEEPROM

The TEI0022 board contains two EEPROMs for configuration and general user purposes.

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titleOn-board configuration EEPROMs overview

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EEPROM ModelI2C AddressDesignatorMemory DensityPurposeNotes
24AA025E48T-I/OT0x50U382 KBitEthernet MAC
93AA56BT-I/OT-U312 KBitJTAG Configuration

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Oscillator

The FPGA module board has following reference clocking source sources provided by an on-board oscillatoroscillators:

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titleReference clock signals

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Clock SourceFrequencySignal Schematic NameClock DestinationNotes
U48, SiT8208AI


25.0 MHz


CLK_25MHz_R

Si5338A PLL U3, Pin 3 (IN3)
HPS_CLK1_25MHzHPS Bank 7A U10, Pin D25
ETH_XTAL_INETH PHY U1, Pin 9
U32, SiT8208AI12.0 MHzOSCIFT2232H U21, Pin 3
U34, SiT8008BI24.0 MHzUSB_CLK24_HUBUSB Hub U33, Pin 33


USB_CLK24_PHYUSB PHY U8, Pin 26


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Scroll Title
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titleProgrammable quad PLL clock generator inputs and outputs

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Si5338A PinSignal Name / DescriptionConnected toDirectionNotes

IN1

SMA_CLK_INSMA J18, Pin 1Input

Assembly option dependent

IN2SMA_CLK_INSMA J18, Pin 21Input

Assembly option dependent

IN3

Reference input clock

U48, Pin 3Input25 MHz oscillator U48, SiT8208

IN4

-GNDInputI2C slave device address LSB

IN5

-

Not ConnectedInputNot used
IN6-GNDInputNot used
SCLHPS_I2C_SCLHPS I2C Bus U10, Pin H23Input

I²C interface muxed to Intel Cyclone V

Slave address: 0x70.

SDAHPS_I2C_SDAHPS I2C Bus U10, Pin A25Input / Output

I²C interface muxed to Intel Cyclone V

Slave address: 0x70.

CLK0A/B

SMA_CLK_OUT_p/n

SMA J7/J10Output

Clock to SMA connectors (Assembly option dependent)

CLK1A/B

CLK_B3B_p/nU10, Pin AF14/15OutputClock to FPGA bank 3B
CLK2ACLK_50MHz_MAX10U41, Pin H6Output

Clock to Intel MAX10 MAX 10 bank 2

CLK2BHPS_CLK2_25MHzU10, Pin F25OutputClock to HPS bank 7A
CLK3A/B

CLK_B4A_p/n

U10, Pin AA16/AB17Output

Clock to FPGA bank 4A


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The TEI0022 uses a precision supply monitor (U54) for three voltages. Therefore, if one of the voltages browns out it should be realized and handled.

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The maximum power consumption of this board mainly depends on the design which is running on the FPGA. Intel provides a power estimator excel sheets to calculate power consumption.

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titlePower Distribution


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Power-On Sequence

The following figures delivers the power-on sequence information. The figure Power Sequency shows the connections between the power devices and its management. The figure Suggested Power Sequency shows the recommended firmware power-on sequence and the figure FMC Power Sequencing shows the firmware dependent FMC power sequence.

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titlePower Sequency


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titleSuggested Power Sequency


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titleFMC Power Sequencing


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Figure_FMC_PWR_PS

Voltage Monitor Circuit

The voltages +3.3V, +5.0V, and VCC are monitored by the voltage monitor circuit LTC2911 (U54), which generates a reset signal at power-on. A manual reset is also possible as described in the reset table.

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