Page History

Template Revision 1.0 - on construction

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Important General Note:

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Export PDF to download, if vivado revision is changed!

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

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Figure template (note: inner scroll ignore/only only with drawIO object):

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Table template:

• Layout macro can be use for landscape of large tables
• Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

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Overview

Refer to http://trenz.org/te0xyz-info for the current online version of this manual and other available documentation.

Key Features

Revision History

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TE0820-test_board-vivado_2019.2-build_3_20200114081551.zip
TE0820-test_board_noprebuilt-vivado_2019.2-build_3_20200114081612.zip

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• initial release

Release Notes and Know Issues

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Requirements

Software

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Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

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Design supports following carriers:

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Additional HW Requirements:

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Content

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For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

• content of the zip file

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Prebuilt

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File

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File-Extension

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Description

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Debian SD-Image

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*.img

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Debian Image for SD-Card

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MCS-File

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*.mcs

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Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

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MMI-File

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*.mmi

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File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

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SREC-File

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*.srec

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Converted Software Application for MicroBlaze Processor Systems

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File

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File-Extension

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Description

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Download

Reference Design is only usable with the specified Quartus version. Do never use different Versions of Quartus software for the same project.

Reference Design is available on:

• TEI0006 "Test Board" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Quartus Design Flow.

See also:

• Project Delivery - Intel devices

The Trenz Electronic FPGA Reference Designs are TCL-script based project. To create project, open project or program device execute "create_project_win.cmd" on Windows OS and "create_project_linux.sh" on Linux OS.

TE Scripts are only needed to generate the quartus project, all other additional steps are optional and can also executed by Intel Quartus/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. Open create_project_win.cmd/create_project_linux.sh and follow instructions in "Messages" section:
   Image Removed
2. Select board in "Board selection" section
3. click on "Create project" button to create project
   
   1. (optional for manual changes) Select correct Quartus install path on "design_basic_settings.cmd"
      Note: Select correct one, see alsoTE Board Part Files
4. Create XSA and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
5. Create Linux (uboot.elf and image.ub) with exported XSA
   
   1. XSA is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
   2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
6. Add Linux files (uboot.elf and image.ub) to prebuilt folder
   
   1. "prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
7. Generate Programming Files with Vitis
   
   1. Run on Vivado TCL: TE::sw_run_vitis -all
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis

Launch

Programming

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
2. Press 0 and enter to start "Module Selection Guide"
   1. Select assembly version
   2. Validate selection
   3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

1. Connect JTAG and power on carrier with module
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
   Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
             optional "TE::pr_program_flash_binfile -swapp hello_te0820" possible
4. Copy image.ub on SD-Card
   • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
   • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
5. Insert SD-Card

SD

1. Copy image.ub and Boot.bin on SD-Card
   • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
   • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
2. Set Boot Mode to SD-Boot.
   • Depends on Carrier, see carrier TRM.
3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

1. Prepare HW like described on section 43680037
2. Connect UART USB (most cases same as JTAG)
3. Select SD Card as Boot Mode (or QSPI - depending on step 1)
   Note: See TRM of the Carrier, which is used.
4. Power On PCB
   Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

1. Open Serial Console (e.g. putty)
   
   1. Speed: 115200
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Linux Console:
   Note: Wait until Linux boot finished For Linux Login use:
   
   1. User Name: root
   2. Password: root
3. You can use Linux shell now.
   1. I2C 0 Bus type: i2cdetect -y -r 0
   2. RTC check: dmesg | grep rtc
   3. ETH0 works with udhcpc
   4. USB type  "lsusb" or connect USB2.0 device
4. Option Features
   1. Webserver to get access to Zynq
      1. insert IP on web browser to start web interface
   2. init.sh scripts
      1. add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)
         

Vivado HW Manager

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

• Control:
• Monitoring:

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Note:

• Description of Block Design, Constrains... BD Pictures from Export...

Block Design

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PS Interfaces

Activated interfaces:

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Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain

set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]]

Software Design - Vitis

For SDK project creation, follow instructions from:

Vitis

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FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2019.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

• Modified Files: blconfig.h, bootloader.c
• Changes:
  
  • Add some console outputs and changed bootloader read address.
  • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2019.2 xilisf_v5_11

• Changed default Flash type to 5.

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Zynq Example:

zynq_fsbl

TE modified 2019.2 FSBL

General:

• Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

• Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

• General Changes: 
  
  • Display FSBL Banner and Device ID

Module Specific:

• Add Files: all TE Files start with te_*
  
  • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
  • CPLD access
  • Read CPLD Firmware and SoC Type
  • Configure Marvell PHY

zynq_fsbl_flash

TE modified 2019.2 FSBL

General:

• Modified Files: main.c
• General Changes:
  
  •  Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

ZynqMP Example:

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zynqmp_fsbl

TE modified 2019.2 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
• Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
• General Changes: 
  
  • Display FSBL Banner and Device Name

Module Specific:

• Add Files: all TE Files start with te_*
  
  • Si5338 Configuration
  • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

• Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
• General Changes:
  
  •  Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

zynqmp_pmufw

Note: Programming and Startup procedure

Programming

Note
Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Get prebuilt boot binaries

1. Run create_project_win.cmd/create_project_linux.sh
2. Select a Module in 'Board selection'
3. Click on the 'Export prebuilt files' button
   1. Folder <project folder>/_binaries_<Article Name> with subfolder boot_linux will be generated and opened

QSPI

1. Connect JTAG and power on carrier with module
2. Open create_project_win.cmd/create_project_linux.sh
3. Select correct board in "Board selection"
4. Click on "Program device" button
   1. if prebuilt files are available: select "Program prebuilt file"
   2. using own generated programming file: select "Program other file" and click on "Browse ..." to open own generated programming file
   3. (optional) click on "Open programmer GUI" to program device with Quartus programmer GUI
5. Click on "Start program device" button

JTAG

Not used on this Example.

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)
3. Connect your board to the network
4. Power on PCB

UART

1. Open Serial Console (e.g. PuTTY)
   1. select COM Port

      Info
      Win OS: see device manager Linux OS: see ls -l dev/serial/by-id  (UART is *USB1)

   2. Speed: 115200
2. Press reset button
3. Console output depends on used Software project, see Software Design - SDK#Application

System Design - Quartus

Scroll Ignore
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Note: Description of Block Design - Project, Block Design - Platform Desginer, ... Block Design Pictures from Export...

Block Design

The block design may differ depending on the assembly variant.

Scroll Title
anchor Figure_BD title-alignment center title Block Design - Platform Designer
Image AddedBlock Design - NIOS_test_board.qsys

Software Design - SDK

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Note: optional chapter separate sections for different apps

Application

Page properties
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General Example:

hello_te0820

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u-boot

U-Boot.elf is generated with PetaLinux. Vitis  is used to generate Boot.bin.

Template location: ./sw_lib/sw_apps/

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Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

• No changes.

U-Boot

Start with petalinux-config -c u-boot

Changes:

• No changes.

Change platform-top.h:

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Device Tree

/include/ "system-conf.dtsi"
/ {
};

Kernel

Start with petalinux-config -c kernel

Changes:

• No changes.

Rootfs

Start with petalinux-config -c rootfs

Changes:

• No changes.

Applications

See: \os\petalinux\project-spec\meta-user\recipes-apps\

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application accemble for Zynq access. Need busybox-httpd

Additional Software

No additional software is needed.

SI5338

File location <design name>/misc/Si5338/Si5338-*.slabtimeproj

General documentation how you work with these project will be available on Si5338

SI5345

File location <design name>/misc/Si5345/Si5345-*.slabtimeproj

General documentation how you work with these project will be available on Si5345

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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Authors

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