Versions Compared

Key

  • This line was added.
  • This line was removed.
  • Formatting was changed.

...

Page properties
hiddentrue
idComments

Notes :

Refer to http://trenz.org/te0xyztei0006-info for the current online version of this manual and other available documentation.

...

Excerpt
  • Quartus 19.4 Pro
  • NIOS II
  • UART
  • ETH
  • QSPI flash memory
  • DDR3L memory
  • User LED

Revision History

Page properties
hiddentrue
idComments

Notes :

  • add every update file on the download
  • add design changes on description

...

Scroll Title
anchorTable_DRH
titleDesign Revision History

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateQuartusProject BuiltAuthorsDescription
2020-03-050919.4 proPro

TE0820TEI0006-test_board-vivadoquartus_201919.2-build_3_202001140815514-20200309134933.zip
TE0820TEI0006-test_board_noprebuilt-vivadoquartus_201919.2-build_3_202001140816124-20200309135555.zip

Thomas Dück
  • initial release


...

Page properties
hiddentrue
idComments

Notes :

  • list of software which was used to generate the design

...

Complete List is available on <design name>/board_files/*_board_filesdevices.csv

Design supports following modules:

Scroll Title
anchorTable_HWM
titleHardware Modules

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TEI0006-02-220-5I01220-2205I-1GBREV01, REV021 GB128 MBNANANA


...

Scroll Title
anchorTable_AHW
titleAdditional Hardware

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

Additional HardwareNotes
USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct type
RJ45 ethernet Cableconnect carrier board to network


Content

Page properties
hiddentrue
idComments

Notes :

  • content of the zip file

For general structure and of the reference design, see Project Delivery - Xilinx Intel devices

Design Sources

Scroll Title
anchorTable_DS
titleDesign sources

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

TypeLocationNotes
Quartus<design name>/source_files/quartusQuartus Project will be generated by TE Scripts
Software<design name>/source_files/softwareAdditional Software will be generated by TE Scripts


...

TE Scripts are only needed to generate the quartus project, all other additional steps are optional and can also executed by Intel Quartus/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

  1. Open create_project_win.cmd/create_project_linux.sh and follow instructions in "Messages" section:
    Create Project GUI - exampleImage Modified
  2. Select board in "Board selection" section
  3. click Click on "Create project" button to create project
    1. (optional for manual changes) Select correct Quartus install path on "design_basic_settings.cmd"


Launch

Page properties
hiddentrue
idComments

Note:

...

  1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
    Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder

...

  1. XSA is exported to "prebuilt\hardware\<short name>"
    Note: HW Export from Vivado GUI create another path as default workspace.
  2. Create Linux images on VM, see PetaLinux KICKstart
    1. Use TE Template from /os/petalinux

...

  1. "prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"

...

  1. Run on Vivado TCL: TE::sw_run_vitis -all
    Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
  2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
    Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis

Launch

Page properties
hiddentrue
idComments

Note:

  • Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
              optional "TE::pr_program_flash_binfile -swapp hello_te0820" possible
  4. Copy image.ub on SD-Card
    • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  5. Insert SD-Card

SD

  1. Copy image.ub and Boot.bin on SD-Card
    • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
    • or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section 43680037
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode (or QSPI - depending on step 1)
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 0 Bus type: i2cdetect -y -r 0
    2. RTC check: dmesg | grep rtc
    3. ETH0 works with udhcpc
    4. USB type  "lsusb" or connect USB2.0 device
  4. Option Features
    1. Webserver to get access to Zynq
      1. insert IP on web browser to start web interface
    2. init.sh scripts
      1. add init.sh script on SD, content will be load automatically on startup (template included in ./misc/SD)

Vivado HW Manager

Page properties
hiddentrue
idComments

Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only
    • SI5338 CLKs:
      • Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz
      • expected CLK Frequ:...

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

  • Control:
  • Monitoring:

...

anchorFigure_VHM
titleVivado Hardware Manager

System Design - Vivado

Page properties
hiddentrue
idComments

Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design

...

anchorFigure_BD
titleBlock Design

PS Interfaces

Page properties
hiddentrue
idComments

Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration

Activated interfaces:

...

anchorTable_PSI
titlePS Interfaces

...

Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain

Code Block
languageruby
title_i_io.xdc
set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]]

Software Design - Vitis

Page properties
hiddentrue
idComments
Note:
  • optional chapter separate

  • sections for different apps

For SDK project creation, follow instructions from:

Vitis

Application

...

hiddentrue
idComments

----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2019.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2019.2 xilisf_v5_11

  • Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

zynq_fsbl

TE modified 2019.2 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY

zynq_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2019.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
  • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2019.2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis  is used to generate Boot.bin.

Template location: ./sw_lib/sw_apps/

...

Software Design -  PetaLinux

Page properties
hiddentrue
idComments
Note:
  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"

For PetaLinux installation and  project creation, follow instructions from:

Config

Start with petalinux-config or petalinux-config --get-hw-description

Changes:

  • No changes.

U-Boot

Start with petalinux-config -c u-boot

Changes:

  • No changes.

Change platform-top.h:

...

languagejs

Device Tree

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
};


Kernel

Start with petalinux-config -c kernel

Changes:

  • No changes.

Rootfs

Start with petalinux-config -c rootfs

Changes:

  • No changes.

Applications

See: \os\petalinux\project-spec\meta-user\recipes-apps\

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application accemble for Zynq access. Need busybox-httpd

...

  • Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

QSPI

  1. Connect JTAG and power on carrier with module
  2. Open "create_project_win.cmd/create_project_linux.sh"
  3. select correct Board in "Board selection" section
  4. Click on "Program device" button
    1. (if prebuilt files are available) select "Program prebuilt file" and click on "Start program device"
    2. select "Program other file" and click on "Browse ..." to open own generated programming file
    3. (optional) click on "Open programmer GUI" to program device with Quartus programmer GUI
  5. Click on "Start program device"

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section TEI0006 Reference Design#Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Power On PCB

UART

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty 
    3. Select "Implicit CR in every LF" in category "Terminal"
  2. Simple Socket Server is starting up. Follow instructions on shell.
    1. If dhcp server is not available: open sdk project in sdk gui and change predefined IP address in simple_socket_server.h, build software project and download *.elf file to device.
    2. Connect your board to the network
    3. Open command shell and enter "telnet <ip_address> 30"

System Design - Quartus

Page properties
hiddentrue
idComments

Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design

Scroll Title
anchorFigure_BD
titleBlock Design - Project
test_board.bdfImage Added


Scroll Title
anchorFigure_BD
titleBlock Design - Platform Designer
NIOS_test_board.qsysImage Added

Software Design - SDK

Page properties
hiddentrue
idComments
Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:

No additional software is needed.

SI5338

File location <design name>/misc/Si5338/Si5338-*.slabtimeproj

General documentation how you work with these project will be available on Si5338

SI5345

File location <design name>/misc/Si5345/Si5345-*.slabtimeproj

General documentation how you work with these project will be available on Si5345

...


  • optional chapter separate

  • sections for different apps

Application

Page properties
hiddentrue
idComments


simple_socket_server

Software example "Simple Socket Server" from SDK software eclipse (modified source files for TEI0006 board).

Template location: <basefolder>/source_files/software/simple_socket_server

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

...

Scroll Title
anchorTable_dch
titleDocument change history.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths2*,*,3*,4*
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateDocument Revision

Authors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
typeFlat

change list
  • initial release 19.4
--all

Page info
infoTypeModified users
dateFormatyyyy-MM-dd
typeFlat

--


Legal Notices

Include Page
IN:Legal Notices
IN:Legal Notices

...