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  • Formatting was changed.


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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"


20220824112022-01-2510 QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
  • corrected Boot Source File in Boot Script-File

  • 2022-01-1492021-06-288
  • added boot process for Microblaze
  • minor typos, formatting2021060172021-05-046 zynq_ from zynq_fsbl5added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export04274Version Historychanged from
    DateVersionChangesAuthor
    2023-06-133.1.
    • Modification from link "available short link"

    ma

    16
    • Design flow:
      • added alternative programming files in Petalinux
    • added chapter FSBL Patch in Software Design - Petalinux
    ma
    2023-06-013.1.15
    • removed u-boot.dtb from
    • Design flow
    ma
    2023-06-013.1.14
    • expandable lists for revision history and supported hardware
    wh
    2023-05-25

    ma

    3.1.
    • extended notes for microblaze boot process with linux

    • add u.boot.dtb to petalinux notes

    • add dtb to prebuilt content

    • replace 20.2 with 21.2

    jh

    13
    • updated according to Vivado 2022.2
    ma
    2023-02-083.1.12
    • removed content of
      • Special FSBL for QSPI programming
    ma

    2022-

    08-

    24

    3.1.

    • carrier reference note
    jh

    11

    • Modification from link "available short link"

    ma

    2022-01-25

    3.1.

    10

    • removed

    • u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin

    • corrected Boot Source File in Boot Script-File

    ma

    2022-01-14

    ma2021-04-28

    3.1.

    9

    • extended notes for microblaze boot process with linux

    • add u.boot.dtb to petalinux notes

    • add dtb to prebuilt content

    • replace 20.2 with 21.2

    jh

    2021-06-283.1.8
    • added boot process for Microblaze
    • minor typos, formatting
    ma
    2021-06-013.1.7
    • carrier reference note
    jh
    2021-05-043.1.6
    • removed zynq_ from zynq_fsbl
    ma
    2021-04-283.1.5
    • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
    • minor typos, formatting
    ma
    2021-04-273.1.4
    • Version History
      • changed from
      • list to table
    • Design flow
      • removed step 5 from Design flow
      • changed link from TE Board Part Files to Vivado Board Part Flow
      • changed cmd shell from picture to codeblock
      • added hidden template for "Copy PetaLinux build image files", depending from hardware
      • added hidden template for "Power on PCB", depending from hardware
    • Usage update of boot process
    • Requirements - Hardware
      • added "*used as reference" for hardware requirements
    • all
      • placed a horizontal separation line under each chapter heading
      • changed title-alignment for tables from left to center
    • all tables
      • added "<project folder>\board_files" in Vivado design sources
    ma

    3.1.3
    • Design Flow
      • formatting
    • Launch
      • formatting
    ma

    3.1.2
    • minor typing corrections
    • replaced SDK by Vitis
    • changed from / to \ for windows paths
    • replaced <design name> by <project folder>
    • added "" for path names
    • added boot.src description
    • added USB for programming
    ma

    3.1.1
    • swapped order from prebuilt files
    • minor typing corrections
    • removed Win OS path length from Design flow, added as caution in Design flow
    ma

    3.1
    • Fix problem with pdf export and side scroll bar
    • update 19.2 to 20.2
    • add prebuilt content option


    3.0
    • add fix table of content
    • add table size as macro
    • removed page initial creator


    Custom_table_size_100


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    Important General Note:

    • Export PDF to download, if vivado revision is changed!

    • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

      • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
        • Figure template (note: inner scroll ignore/only only with drawIO object):

          Scroll Title
          anchorFigure_xyz
          titleText


          Scroll Ignore

          Create DrawIO object here: Attention if you copy from other page, use


          Scroll Only

          image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



        • Table template:

          • Layout macro can be use for landscape of large tables
          • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)

        • Scroll Title
          anchorTable_xyz
          titleText

          Scroll Table Layout
          orientationportrait
          sortDirectionASC
          repeatTableHeadersdefault
          style
          widths
          sortByColumn1
          sortEnabledfalse
          cellHighlightingtrue

          ExampleComment
          12



    • ...

    Overview

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    Notes :

    ZynqMP PS Design with Linux Example and simple frequency counter to measure SI5338 Reference CLK with Vivado HW-Manager.
    Wiki Resources page: http://trenz.org/te0823-info

    Key Features

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    Notes :

    • Add basic key futures, which can be tested with the design


    Excerpt
    • Vitis/Vivado 20212022.2.1
    • PetaLinux
    • SD
    • ETH
    • USB
    • I2C
    • RTC
    • FMeter
    • MAC from EEPROM
    • User LED
    • Modified FSBL for SI5338 programming
    • Special FSBL for QSPI programming

    Revision History

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    Notes :

    • add every update file on the download
    • add design changes on description


    Expand
    titleExpand List
    Scroll Title
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    titleDesign Revision History

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    DateVivadoProject BuiltAuthorsDescription
    2022
    2023-
    11
    09-
    08
    20
    2021
    2022.2
    .1
    TE0823-test_board
    _noprebuilt
    -vivado_2022.2-build_8_20230920091958.zip
    TE0823-test_board_noprebuilt-vivado_2022.2-build_8_20230920091958.zip
    Manuela Strücker
    • Release Vivado 2022.2
    • new variants
    2022-11-082021.2.1TE0823-test_board_noprebuilt-vivado_2021.2-build_20_20221108082219.zip
    TE0823-test_board-vivado_2021.2-build_20_20221108082219.zip
    Manuela Strücker
    • bugfix uncomment block design modifications in mod_bd.tcl
    • added jtag2axi for test purposes
    2022-10-252021.2.1TE0823-test_board_noprebuilt-vivado_2021.2-build_19_20221025110452.zip
    TE0823-test_board-vivado_2021.2-build_19_20221025110452.zip
    Manuela Strücker
    • Release Vivado 2021.2.1

    • script update

    2021-10-272020.2TE0823-test_board_noprebuilt-vivado_2020.2-build_8_20211027094814.zip
    TE0823-test_board-vivado_2020.2-build_8_20211027094802.zip
    Mohsen Chamanbaz/John Hartfiel
    • replace 19.2 fsbl template with 20.2
    • new variants
    2021-08-242020.2TE0823-test_board_noprebuilt-vivado_2020.2-build_7_20210824103952.zip
    TE0823-test_board-vivado_2020.2-build_7_20210824103936.zip
    Mohsen Chamanbaz
    • startup application added
    • webfwu application added
    2021-08-172020.2TE0823-test_board_noprebuilt-vivado_2020.2-build_7_20210817113507.zip
    TE0823-test_board-vivado_2020.2-build_7_20210817113435.zip
    Mohsen Chamanbaz
    • 2020.2 release
    2020-03-162019.2TE0823-test_board-vivado_2019.2-build_8_20200316163150.zip
    TE0823-test_board_noprebuilt-vivado_2019.2-build_8_20200316163202.zip
    John Hartfiel
    • initial release



    Release Notes and Know Issues

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    Notes :
    • add known Design issues and general notes for the current revision
    • do not delete known issue, add fixed version time stamp if  issue fixed


    Scroll Title
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    titleKnown Issues

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    IssuesDescriptionWorkaroundTo be fixed version
    Xilinx SoftwareIncompatibility of board files for ZynqMP with eMMC activated for Vivado versions below/equal to 2021.2 and 2021.2.1 patch, see Xilinx Forum Requestuse corresponding board files for the Vivado versions--


    Requirements

    Software

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    Notes :

    • list of software which was used to generate the design


    Scroll Title
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    titleSoftware

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    SoftwareVersionNote
    Vitis20212022.2.1needed
    Vivado is included into Vitis installation
    PetaLinux20212022.2needed
    SI ClockBuilder Pro---optional


    Hardware

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    Notes :

    • list of hardware which was used to generate the design
    • mark the module and carrier board, which was used tested with an *

    Basic description of TE Board Part Files is available on TE Board Part Files.

    Complete List is available on "<project folder>\board_files\*_board_files.csv"

    Design supports following modules:


    Expand
    titleExpand List
    Scroll Title
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    titleHardware Modules

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    Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
    TE0823-01-3PIU1FL 3cg_1li_1gbREV01   1GB      128MB     8GB        NA                     Low Profile Connector
    TE0823-01-3PIU1FA3cg_1li_1gbREV01 1GB 128MB  8GB   NANA
    TE0823-01-S0013cg_1li_2gbREV012GB128MB8GBNACustom, AN:3PI?1FA
    TE0823-01-3PIU1ML3cg_1li_1gbREV011GB128MB8GBNALow Profile Connector, other emmC Manuf.
    TE0823-01-3PIU1MA3cg_1li_1gbREV011GB128MB8GBNAother emmC Manuf.
    TE0823-01-S0023cg_1li_2gbREV012GB128MB8GBNACustom, other emmC Manuf., AN:3PI?1FA

    *used as reference

    Design supports following carriers:

    TE0823-01-3PIU1MAZ3cg_1li_1gbREV011GB128MB8GBNAother emmC Manuf.
    TE0823-01-S0033cg_1li_2gbREV012GB128MB8GBNACustom, other emmC Manuf., AN:3PI?1FA

    *used as reference


    Design supports following carriers:

    Scroll Title
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    titleHardware Carrier

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    Carrier ModelNotes
    TE0701
    TE0703*
    TE0705
    TE0706
    TEBA0841
    • Important: See restrictions on usage with 7 Serie Carriers: 4 x 5 SoM Carriers
    • No SD Slot available, pins goes to Pin Header
    • For TEBA0841 REV01, please contact TE support
    TEF1001TEF1002

    *used as reference

    Additional HW Requirements:

    Scroll Title
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    titleAdditional Hardware

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    Additional HardwareNotes
    USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct typtype
    XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI
    CoolerIt's recommended to use cooler on ZynqMP device

    *used as reference

    Content

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    Notes :

    • content of the zip file

    For general structure and of the reference design, see Project Delivery - AMD devices

    Design Sources

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    titleDesign sources

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    TypeLocationNotes

    Vivado

    <project folder>\block_design
    <project folder>\constraints
    <project folder>\ip_lib
    <project folder>\board_files

    Vivado Project will be generated by TE Scripts

    Vitis

    <project folder>\sw_lib

    Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation

    PetaLinux

    <project folder>\os\petalinux

    PetaLinux template with current configuration


    Additional Sources

    Scroll Title
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    title-alignmentcenter
    titleAdditional design sources

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    TypeLocationNotes

    SI5338

    <project folder>\misc\PLL\Si5338

    SI5338 Project with current PLL Configuration

    init.sh

    <project folder>\misc\sd

    Additional Initialization Script for Linux



    Prebuilt

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    Notes :

    • prebuilt files

    • Template Table:


      • Scroll Title
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        titlePrebuilt files

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        File

        File-Extension

        Description

        BIF-File*.bifFile with description to generate Bin-File
        BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
        BIT-File*.bitFPGA (PL Part) Configuration File
        Boot Script-File*.scr

        Distro Boot Script file

        DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

        Debian SD-Image

        *.img

        Debian Image for SD-Card

        Diverse Reports---Report files in different formats
        Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
        Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
        LabTools Project-File*.lprVivado Labtools Project File

        MCS-File

        *.mcs

        Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

        MMI-File

        *.mmi

        File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

        OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
        Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

        SREC-File

        *.srec

        Converted Software Application for MicroBlaze Processor Systems




    Scroll Title
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    titlePrebuilt files (only on ZIP with prebult content)

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    cellHighlightingtrue

    File

    File-Extension

    Description

    BIF-File*.bifFile with description to generate Bin-File
    BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
    BIT-File*.bitFPGA (PL Part) Configuration File
    Boot Script-File*.scr

    Distro Boot Script file

    DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
    Diverse Reports---Report files in different formats
    Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
    Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
    LabTools Project-File*.lprVivado Labtools Project File
    OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
    Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


    Download

    Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

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    Reference Design is available on:

    Design Flow

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    Notes :
    • Basic Design Steps

    • Add/ Remove project specific description


    Note

    Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

    See also:

    The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

    TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

    Note

    Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")


    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

      Code Block
      languagebash
      themeMidnight
      title_create_win_setup.cmd/_create_linux_setup.sh
      ------------------------Set design paths----------------------------
      -- Run Design with: _create_win_setup
      -- Use Design Path: <absolute project path>
      --------------------------------------------------------------------
      -------------------------TE Reference Design---------------------------
      --------------------------------------------------------------------
      -- (0)  Module selection guide, project creation...prebuilt export...
      -- (1)  Create minimum setup of CMD-Files and exit Batch
      -- (2)  Create maximum setup of CMD-Files and exit Batch
      -- (3)  (internal only) Dev
      -- (4)  (internal only) Prod
      -- (c)  Go to CMD-File Generation (Manual setup)
      -- (d)  Go to Documentation (Web Documentation)
      -- (g)  Install Board Files from Xilinx Board Store (beta)
      -- (a)  Start design with unsupported Vivado Version (beta)
      -- (x)  Exit Batch (nothing is done!)
      ----
      Select (ex.:'0' for module selection guide):


    2. Press 0 and enter to start "Module Selection Guide"
    3. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
      • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

        Note

        Note: Select correct one, see also Vivado Board Part Flow


    4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

      Code Block
      languagepy
      themeMidnight
      titlerun on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
      TE::hw_build_design -export_prebuilt


      Info

      Using Vivado GUI is the same, except file export to prebuilt folder.


    5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
      • use TE Template from "<project folder>\os\petalinux"
      • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

      • The build images are located in the "<plnx-proj-root>/images/linux" directory

    6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr
    7. Generate Programming Files with Vitis (recommended)
      1. Copy PetaLinux build image files to prebuilt folder
        • copy u-boot.elf,

      u-boot
        • system.dtb,

      system
        • bl31.

      dtb
        • elf, image.ub

      , bl31.elf
        • and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

          Info

          "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"


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          This step depends on Xilinx Device/Hardware

          for Zynq-7000 series

          • copy u-boot.elf
      , u-boot.dtb
          • , system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

          for ZynqMP

          • copy u-boot.elf,
      u-boot.dtb,
          • system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

          for Microblaze

          • ...
      Generate

      1. Generate Programming Files with Vitis
        Code Block
        languagepy
        themeMidnight
        titlerun on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
        TE::sw_run_vitis -all
        TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


        Note

        TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis

    Launch


    1. Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart

    Launch

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    Note:

    • Programming and Startup procedure

    Programming

    Note

    Check Module and Carrier TRMs for proper HW configuration before you try any design.

    Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

    Note: Depending on CPLD Firmware and Boot Mode settings, QSPI boot with Linux image on SD or complete SD Boot is possible.

    Get prebuilt boot binaries

    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
    2. Press 0 and enter to start "Module Selection Guide"
      1. Select assembly version
      2. Validate selection
      3. Select Create and open delivery binary folder

        Info

        Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


    QSPI-Boot mode

          Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

    1. Connect JTAG and power on carrier with module
    2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

      Code Block
      languagepy
      themeMidnight
      titlerun on Vivado TCL (Script programs BOOT.bin on QSPI flash)
      TE::pr_program_flash -swapp u-boot
      TE::pr_program_flash -swapp hello_te0823 (optional)


    3. Copy image.ub and boot.scr on SD or USB
      • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
      • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
    4. Set Boot Mode to QSPI-Boot and insert SD or USB.
      • Depends on Carrier, see carrier TRM.

    SD-Boot mode

    1. Copy image.ub, boot.src and Boot.bin on SD
      • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
      • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
    2. Set Boot Mode to SD-Boot.
      • Depends on Carrier, see carrier TRM.
    3. Insert SD-Card in SD-Slot.

    JTAG

    Not used on this Example.

    Usage

    1. Prepare HW like described on section Programming
    2. Connect UART USB (most cases same as JTAG)
    3. Select SD Card or QSPI as Boot Mode (Depends on used programming variant)

      Info

      Note: See TRM of the Carrier, which is used.


      Tip

      Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
      The boot options described above describe the common boot processes for this hardware; other boot options are possible.
      For more information see Distro Boot with Boot.scr


    4. Power On PCB

      Expand
      titleboot process

      1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from SD/QSPI Flash into OCM

      2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR,

      3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


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      This step depends on Xilinx Device/Hardware

      for Zynq-7000 series

      1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

      2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,

      3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


      for ZynqMP???

      1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

      2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

      3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


      for Microblaze

      1. FPGA Loads Bitfile from Flash,

      2. MCS Firmware configure SI5338 and starts Microblaze,

      3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),

      4. U-boot loads Linux from QSPI Flash into DDR


      for native FPGA

      ...


    Linux

    1. Open Serial Console (e.g. putty)
      • Speed: 115200
      • Select COM Port

        Info

        Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)


    2. Linux Console:

      Code Block
      languagebash
      themeMidnight
      # password default disabled with 2021.2 petalinux release
      petalinux login: root
      Password: root


      Info

      Note: Wait until Linux boot finished


    3. You can use Linux shell now.

      Code Block
      languagebash
      themeMidnight
      i2cdetect -y -r 0	(check I2C 0 Bus)
      dmesg | grep rtc	(RTC check)
      udhcpc				(ETH0 check)
      lsusb				(USB check)


    4. Option Features

      • Webserver to get access to Zynq

        • insert IP on web browser to start web interface

      • init.sh scripts

        • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")


    Vivado HW Manager

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    Note:

    • Add picture of HW Manager

    • add notes for the signal either groups or topics, for example:

      Control:

      • add controllable IOs with short notes..

      Monitoring:

      • add short notes for signals which will be monitored only
      • SI5338
      _CLK0 Counter
      • CLKs:
       
        • Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
            • Set radix from VIO signals to unsigned integer.
              Note: Frequency Counter is inaccurate and displayed unit is Hz
            • expected CLK Frequency...
      Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).

      Control:

      • GTR Power: set X0=0 and X1=1 to disable GTR Power
      • USER LED: On/OFF

      Monitoring:

      • SI5338_CLK0 Counter:  200MHz with example Design
        • Set radix from VIO signals to unsigned integer.
          Note: Frequency Counter is inaccurate and displayed unit is Hz
      • ETH PHY LEDs


      Scroll Title
      anchorFigure_VHM
      title-alignmentcenter
      titleVivado Hardware Manager


      System Design - Vivado

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      Note:

      • Description of Block Design, Constrains... BD Pictures from Export...

      Block Design

      Scroll Title
      anchorFigure_BD
      title-alignmentcenter
      titleBlock Design

      draw.io Diagram
      bordertrue
      diagramNameTE0823_block_design
      simpleViewerfalse
      width1000
      linksauto
      tbstyletop
      diagramDisplayName
      lboxtrue
      diagramWidth1369
      revision1



      PS Interfaces

      Page properties
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      Note:

      • optional for Zynq / ZynqMP only

      • add basic PS configuration

      Activated interfaces:

      Scroll Title
      anchorTable_PSI
      title-alignmentcenter
      titlePS Interfaces

      Scroll Table Layout
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      cellHighlightingtrue


      TypeNote
      DDR
      QSPIMIO
      SD0MIO
      SD1MIO
      I2C0MIO
      UART0MIO
      GPIO0MIO
      SWDT0..1
      TTC0..3
      GEM3MIO
      USB0MIO, USB2 only



      Constrains

      Basic module constrains

      Code Block
      languageruby
      title_i_bitgen_common.xdc
      set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
      set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design

      Design specific constrain

      Code Block
      languageruby
      title_i_io.xdc
      set_property PACKAGE_PIN K9 [get_ports {SI5338_CLK0_D_clk_p[0]}]
      set_property IOSTANDARD LVDS [get_ports {SI5338_CLK0_D_clk_p[0]}]
      set_property DIFF_TERM TRUE [get_ports {SI5338_CLK0_D_clk_p[0]}]
      
      set_property PACKAGE_PIN B13 [get_ports {x0[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {x0[0]}]
      set_property PACKAGE_PIN B14 [get_ports {x1[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {x1[0]}]
      
      set_property PACKAGE_PIN C13 [get_ports {PHY_LED[0]}]
      set_property PACKAGE_PIN C14 [get_ports {PHY_LED[1]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {PHY_LED*}]
      set_property PACKAGE_PIN A15 [get_ports {USRLED[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {USRLED*}]
      set_property PACKAGE_PIN B14 [get_ports {x1[0]}]
      set_property IOSTANDARD LVCMOS18 [get_ports {x1[0]}]

      Software Design - Vitis

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      Note:
      • optional chapter separate

      • sections for different apps

      For Vitis project creation, follow instructions from:

      Vitis

      Application

      Page properties
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      ----------------------------------------------------------

      FPGA Example

      scu

      MCS Firmware to configure SI5338 and Reset System.

      srec_spi_bootloader

      ----------------------------------------------------------

      scu

      MCS Firmware to configure SI5338 and Reset System.

      srec_spi_bootloader

      TE modified 2022.2 TE modified 2021.2 SREC

      Bootloader to load app or second bootloader from flash into DDR

      Descriptions:

      • Modified Files: blconfig.h, bootloader.c
      • Changes:
        • Add some console outputs and changed bootloader read address.
        • Add bugfix for 2018.2 qspi flash

      xilisf_v5_11

      TE modified 20212022.2 xilisf_v5_11

      • Changed default Flash type to 5.

      ----------------------------------------------------------

      Zynq Example:

      fsbl

      TE modified 2021.2 FSBL

      General:

      ----------------------------------------------------------

      fsbl

      TE modified 2022.2 FSBL

      General:

      • Modified Files: main.c, fsbl_hooks.Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
      • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

      • General Changes: 
        • Display FSBL Banner and Device ID

      Module Specific:

      • Add Files: all TE Files start with te_*
        • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
        • CPLD access
        • Read CPLD Firmware and SoC Type
        • Configure Marvell PHY
      fsbl_flash

      TE modified 2021.2 FSBL

      General:

      • Modified Files: main.c
      • General Changes:
        • Display FSBL Banner
        • Set FSBL Boot Mode to JTAG
        • Disable Memory initialisation

      ZynqMP Example:


      ----------------------------------------------------------

      ZynqMP Example:

      ----------------------------------------------------------

      zynqmpzynqmp_fsbl

      TE modified 20212022.2 FSBL

      General:

      • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
      • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
      • General Changes: 
        • Display FSBL Banner and Device Name

      Module Specific:

      • Add Files: all TE Files start with te_*
        • Si5338 Configuration
        • ETH+OTG Reset over MIO

      zynqmp_

      fsbl_flash

      pmufw

      Xilinx default PMU firmware.

      ----------------------------------------------------------

      General Example:

      TE modified 2021.2 FSBL

      General:

      • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
      • General Changes:
        • Display FSBL Banner
        • Set FSBL Boot Mode to JTAG
        • Disable Memory initialisation

      zynqmp_pmufw

      Xilinx default PMU firmware.

      ----------------------------------------------------------

      General Example:

      hello_te0820

      Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

      u-boot

      U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

      Template location: "<project folder>\sw_lib\sw_apps\"

      zynqmp_fsbl

      TE modified 20212022.2 FSBL

      General:

      • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
      • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
      • General Changes: 
        • Display FSBL Banner and Device Name

      Module Specific:

      • Add Files: all TE Files start with te_*
        • Si5338 Configuration
        • ETH+OTG Reset over MIO

      zynqmp_

      fsbl_flash

      pmufw

      Xilinx default PMU firmware.

      hello

      TE modified 2021.2 FSBL

      General:

      • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
      • General Changes:
        • Display FSBL Banner
        • Set FSBL Boot Mode to JTAG
        • Disable Memory initialisation

      zynqmp_pmufw

      Xilinx default PMU firmware.

      hello_te0823

      Hello TE0823 is a Xilinx Hello World example as endless loop instead of one console output.

      u-boot

      U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

      Software Design -  PetaLinux

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      Page properties
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      Note:
      • optional chapter separate

      • sections for linux

      • Add "No changes." or "Activate: and add List"

      For PetaLinux installation and  project creation, follow instructions from:

      Config

      Start with petalinux-config or petalinux-config --get-hw-description

      Changes:

      • select SD default instead of eMMC:
        • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
        generate u-boot.dtb:
        •  CONFIG_SUBSYSTEM_UBOOT_EXT_DTB=y
      • add new flash partition for bootscr and sizing
        • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0x2000000
        • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART1_SIZE=0x2000000
        • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x20000000x40000
        • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
        • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000

      U-Boot

      • Identification
        • CONFIG_SUBSYSTEM_HOSTNAME="trenz"
        • CONFIG_SUBSYSTEM_PRODUCT="TE0823"

      U-Boot

      Start with petalinux-config -c u-boot
      Changes:

      • MAC from eeprom together with uboot and device tree settings:
        • CONFIG_ENV_OVERWRITE=y
        • CONFIG_ZYNQ_GEMMAC_I2C_MAC_OFFSET=0xFAIN_EEPROM is not set
        • CONFIG_SYSNET_I2C_EEPROM_ADDR=0x50RANDOM_ETHADDR is not set
      • Boot Modes:
        • CONFIG_QSPI_BOOT=y
        • CONFIG_SD_BOOT=y
        • CONFIG_ENV_IS_IN_FAT is not set
        • # CONFIG_ENV_IS_IN_NAND is not set
        • CONFIG_ENV_IS_IN_SPI_FLASH is not set
        • CONFIG_SYS_REDUNDAND_ENVIRONMENT is not set
        • CONFIG_BOOT_SCRIPT_OFFSET=0x4040000
      • Identification
        • CONFIG_IDENT_STRING=" TE0823"


      Change platform-top.h:

      Code Block
      languagejs
      #include <configs/xilinx_zynqmp.h>
      #no changes

      Device Tree

      Code Block
      languagejs
      titleproject-spec\meta-user\recipes-bsp\device-tree\files\system-user.dtsi
      /include/ "system-conf.dtsi"
      
      
      /*------------------------- QSPISD1 sd2.0 ------------------------- */
      &qspisdhci1 {
          #address-cells = <1>;
          #size-cells = <0>;disable-wp;
          no-1-8-v;
      };
      
      
      /*----------------------- USB 2.0 only --------------------*/
      &dwc3_0 {
          status = "okay";
          flash0: flash@0 {dr_mode = "host";
              //compatiblemaximum-speed = "flash name, "micron,m25p80"high-speed";
          /delete-property/phy-names;
          compatible = "jedec,spi-nor"/delete-property/phys;
          /delete-property/snps,usb3_lpm_capable;
          reg = <0x0>snps,dis_u2_susphy_quirk;
          snps,dis_u3_susphy_quirk;
      };
      
      &usb0 {
          #address-cellsstatus = <1>"okay";
           /delete-property/ clocks;
          #size-cells/delete-property/ clock-names;
          clocks = <1><0x3 0x20>;
          }clock-names = "bus_clk";
      };
      
      
      /*------------------------- SD1ETH sd2.0PHY -----------------------*/
      &sdhci1gem3 {
          disable-wp /delete-property/ local-mac-address;
          no-1-8-v;
      };
      
      
      /*------------------------- ETH PHY -----------------------*/
      &gem3 {
          phy-handle = <&phy0>;
          
          nvmem-cells = <&eth0_addr>;
          nvmem-phy-handle = <&phy0>;
          
          nvmem-cells = <&eth0_addr>;
          nvmem-cell-names = "mac-address";
          
          phy0: phy0@1 {
              device_type = "ethernet-phy";
              reg = <1>;
          };
      };
      
      
      /*------------------------- USB 2.0 only QSPI ----------------------*/--- */
      &dwc3_0qspi {
          status#address-cells = "okay"<1>;
          dr_mode#size-cells = "host"<0>;
          maximum-speedstatus = "high-speedokay";
          /delete-property/phy-names;
          /delete-property/phys;
      flash0: flash@0 {
            /delete-property/snps,usb3_lpm_capable;
        compatible = snps,dis_u2_susphy_quirk"jedec,spi-nor";
           snps,dis_u3_susphy_quirk;
      };
         reg 
      &usb0 {= <0x0>;
          status = "okay";
        #address-cells  /delete-property/ clocks= <1>;
          /delete-property/ clock-names;
          clocks#size-cells = <0x3 0x20><1>;
          clock-names = "bus_clk"};
      };
      
      
      /*---------------------------- I2C ------------------------*/
      &i2c0 {
          eeprom: eeprom@50 {
              compatible = "microchip,24aa025", "atmel,24c02";
              reg = <0x50>;
              
              #address-cells = <1>;
              #size-cells = <1>;
              eth0_addr: eth-mac-addr@FA {
                reg = <0xFA 0x06>;
           };     };
           
        };
      };
           
      Code Block
      languagejs
      titleproject-spec\meta-user\recipes-bsp\uboot-device-tree\files\system-user.dtsi
      /include/ "system-conf.dtsi"
      
      
      /*------------------------- QSPI ------------------------- */
      &qspi {
          #address-cells = <1>;
          #size-cells = <0>;
          status = "okay";
          flash0: flash@0 {
              //compatible = "flash name, "micron,m25p80";
              compatible = "jedec,spi-nor";
              reg = <0x0>;
              #address-cells = <1>;
              #size-cells = <1>;
          };
      };
      
      
      /*----------------------- SD1 sd2.0 -----------------------*/
      &sdhci1 {
          disable-wp;
          no-1-8-v;
      };
      
      
      /*------------------------- ETH PHY -----------------------*/
      &gem3 {
          phy-handle = <&phy0>;
          
          nvmem-cells = <&eth0_addr>;
          nvmem-cell-names = "mac-address";
          
          phy0: phy0@1 {
              device_type = "ethernet-phy";
              reg = <1>;
          };
      };
      
      
      /*----------------------- USB 2.0 only --------------------*/
      &dwc3_0 {
          status = "okay";
          dr_mode = "host";
          maximum-speed = "high-speed";
          /delete-property/phy-names;
          /delete-property/phys;
          /delete-property/snps,usb3_lpm_capable;
          snps,dis_u2_susphy_quirk;
          snps,dis_u3_susphy_quirk;
      };
          
      &usb0 {
          status = "okay";
          /delete-property/ clocks;
          /delete-property/ clock-names;
          clocks = <0x3 0x20>;
          clock-names = "bus_clk";
      };
      
      
      /*---------------------------- I2C ------------------------*/
      &i2c0 {
        eeprom: eeprom@50 {
           compatible = "microchip,24aa025", "atmel,24c02";
           reg = <0x50>;
           
           #address-cells = <1>;
           #size-cells = <1>;
           eth0_addr: eth-mac-addr@FA {
             reg = <0xFA 0x06>;
           };     
           
        };
      };
          

      FSBL patch

      Must be add manually, see template

      Kernel

      Start with petalinux-config -c kernel

      Changes:

      • Only needed to fix JTAG Debug issue:

        • CONFIG_CPU_IDLE is not set

        • CONFIG_CPU_FREQ is not set

        • CONFIG_EDAC_CORTEX_ARM64=y

      Rootfs

      Start with petalinux-config -c rootfs

      Changes:

    • For web server app:
      • CONFIG_busybox-httpd=y
    • Kernel

      Start with petalinux-config -c kernel

      Changes:

      • Only needed to fix JTAG Debug issue:

        • CONFIG_CPU_FREQ is not set

      Rootfs

      Start with petalinux-config -c rootfs

      Changes:

      • For web server app:
        • CONFIG_busybox-httpd=y
      • For additional test tools only:
        • CONFIG_i2c-tools=y
        • CONFIG_packagegroup-petalinux-utils=y    (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
      • For auto login:
        • CONFIG_auto-login=y
        • CONFIG_ADD_EXTRA_USERS="root:root;petalinux:;"

      FSBL patch (alternative for vitis fsbl trenz patch)

      See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"

      te_* files are identical to files in "<project folder>\sw_lib\sw_apps\zynqmp_fsbl\src" except for the PLL files (SI5338) which depend on PLL revision. The PLL files may have to be copied again manually into the appropriate petalinux folder "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw\fsbl-firmware\git\lib\sw_apps\zynqmp_fsbl\src"

      For additional test tools only:
    • CONFIG_i2c-tools=y
    • CONFIG_packagegroup-petalinux-utils=y    (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)

      Applications

      See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

      startup

      Script App to load init.sh from SD Card if available.

      webfwu

      Webserver application suitable for Zynq access. Need busybox-httpd

      Additional Software

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      Note:
      • Add description for other Software, for example SI CLK Builder ...
      • SI5338 and SI5345 also Link to:

      SI5338

      File location "<project folder>\misc\PLL\Si5338\Si5338-*.slabtimeproj"

      General documentation how you work with these project will be available on Si5338

      Appx. A: Change History and Legal Notices

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      Document Change History

      To get content of older revision  got to "Change History"  of this page and select older document revision number.

      Page properties
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      • Note this list must be only updated, if the document is online on public doc!
      • It's semi automatically, so do following
        • Add new row below first

        • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

        • Metadata is only used of compatibility of older exports


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      DateDocument RevisionAuthorsDescription

      Page info
      modified-date
      modified-date
      dateFormatyyyy-MM-dd

      Page info
      current-version
      current-version
      prefixv.

      Page info
      modified-user
      modified-user

      • Release Vivado 2022.2
      • new variants
      2022-11.18v.13Manuela Strücker
      • bugfix uncomment block design modifications in mod_bd.tcl
      • added jtag2axi for test purposes
      2022-10-25v.11Manuela Strücker
      • Release Vivado 2021.2.1

      • script update

      2022-10-27v.9John Hartfiel
      • new design files and variants
      2021-08-24v.8John Hartfiel
      • startup application added
      • webfwu application added
      2021-08-18v.7Mohsen Chamanbaz
      • 2020.2 release
      2020-03-17v.4John Hartfiel
      • 2019.2 release

      All

      Page info
      modified-users
      modified-users



      Legal Notices

      Include Page
      IN:Legal Notices
      IN:Legal Notices



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