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changes.mady.by.user Martin Rohrmüller

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changes.mady.by.user John Hartfiel

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A 25.000000 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks. It is possible to use the clocks connected to the GTR bank in the user's logic design. This is achieved by instantiating a IBUFDSGTE buffer in the design.

Once running, the frequency and other parameters can be changed by programming the device using the I2C bus connected between the FPGA (master) and clock generator (slave). For this, proper I2C bus logic has to be implemented in FPGA.

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  • Corrected PLL section
2020-02-03v.85Martin Rohrmüller
  • Corrected #MIOs for QSPI and USB in block diagrammdiagram
2019-11-28v.81Martin Rohrmüller
  • typo and designator in section USB interface corrected
2019-10-30v.80John Hartfiel
  • typo correction
2019-09-17v79Martin Rohrmüller
  • Updated according to PCN-20190110: eMMC, QSPI-Flash

2019-07-17

v.78Martin Rohrmüller
  • Corrected PJTAG Mio Pin29 in table 8

2019-05-08

v.77John Hartfiel
  • Corrected EEPROM I2C Address
  • Correction USB PHY connection

2018-11-12

v.74

John Hartfiel
  • update boot section

2018-08-30

v.73John Hartfiel
  • typo correction
  • update CPLD section
  • add LEDs to component list
  • add 3D picture of REV03 instead of REV01 picture

2018-07-12

v.69Ali Naseri
  • Update PCB Rev03

2018-06-11

v.61John Hartfiel
  • Rework chapter currently available products
  • add PJTAG note to MIOtable
2018-03-12v.54
  • Correction Power Rail Section
2017-11-20v.51John Hartfiel
  • Correction Default MIO Configuration Table
2017-11-10v.50John Hartfiel
  • Replace B2B connector section
2017-10-18v.49John Hartfiel
  • add eMMC section
2017-09-25v.48John Hartfiel
  • Correction in the "Board to Board (B2B) I/Os" section
  • Update in the "Variants Currently In Production" section
2017-09-18v.47John Hartfiel
  • Update PS MIO table
2017-08-30v.46Jan Kumann
  • MGT lanes section added.

2017-08-24

v.36

John Hartfiel
  • Correction in the  "Key Features" section.
2017-08-21v.34John Hartfiel
  • "Initial delivery state" section updated.
2017-08-21v.33Jan Kumann
  • HW revision 02 block diagram added.
  • Power distribution and power-on sequence diagram added.
  • System Controller CPLD and DDR4 SDRAM sections added.
  • TRM update to the template revision 1.6
  • Weight section removed.
  • Few minor corrections.



2017-08-18


v.7

John Hartfiel
  • Style changes
  • Updated "Boot Mode", "HW Revision History", "Variants Currently In Production" sections
  • Correction of MIO SD Pin-out, System Controller chapter
  • Update and new sub-sections on "On Board Peripherals and Interfaces" sections

2017-08-07

v.5

Jan Kumann

  • Initial version
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