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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modules and mainboards:

  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2...ZU5*
    • Engine: CG, EG, EV*
    • Speed: -1LI, -2LE,*, **
    • Temperature: I, E,*, **
  • RAM/Storage
    • Low Power DDR4 on PS
      • Data width: 32bit
      • Size: def. 2GB*
      • Speed:***
    • eMMC
      • Data width: 8Bit
      • size: def. 8GB *
    • QSPI boot Flash in dual parallel mode (size depends on assembly version)
      • Data width: 8bit
      • size: def. 128MB *
    • HyperRAM/Flash (optional, default not assembled)
      • size:*
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • Lattice LCMXO2
    • PLL SI5338
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
  • Interface
    • 132 x HP PL I/Os (3 banks)
    • ETH
    • USB
    • 4 GTR (for USB3, Sata, PCIe, DP)
    • MIO for UART
    • MIO for SD
    • MIO for PJTAG
    • JTAG
    • Ctrl
  • Power
    • 3.3V-5V Main Input
    • 3.3V Controller Input
    • Variable Bank IO Power Input
  • Dimension
    • 4 cm x 5 cm
  • Notes
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination


Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension
  • <Replace for module use "SoC/FPGA" for Carrier "Modules">
    • ...
  • RAM/Storage
    • ...
  • On Board
    • ...
  • Interface
    • ...
  • Power
    • ...
  • Dimension
    • ...
  • Notes
    • ...


  • SoC/FPGA
    • Xilinx Zynq UltraScale+ XCZU3EG-1SFVC784I
      • ZU3EG, 784 Pin Packages
      • Application Processor: Quad-Core ARM Cortex-A53 MPCore
      • Real-Time Processor: Dual-core ARM Cortex-R5 MPCore
      • Graphics Processor: Mali-400 MP2
  • RAM/Storage
    • 2 GByte DDR4 SDRAM, 32-Bit databus-width
    • 128 MByte QSPI boot Flash in dual parallel mode
    • 8 GByte e.MMC Memory (up to 64 GByte)
    • MAC address serial EEPROM with EUI-48 node identity
  • On Board
    • Graphic Processing Unit (GPU) :Mali-400 MP2
  • Interface
    • PCI Express interface version 2.1 compliant
    • SATA 3.1 specification compliant interface
    • DisplayPort source-only interface with video resolution up to 4k x 2k

    • USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
    • 1 GB/s serial GMII interface
    • Hi-speed USB2 ULPI transceiver with full OTG support
    • 34 x High Performance und 96 x High Density PL I/Os
    • 14 x PS MIOs (6 of the MIOs intended for SD card interface in default configuration)
    • 4 x serial PS GTR transceivers
    • Rugged for shock and high vibration
  • Power
    • All power supplies on board
  • Dimension
    • 40 x 50 mm

Block Diagram

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Note

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Scroll Title
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titleTExxxx block diagramTE0821 block diagram


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Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .



Figure
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titleTE0821 main components


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_OV_MC
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  1. ...
  2. ...
  3. ...

Initial Delivery State

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titleBoot process.

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MODE Signal State

Boot Mode








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titleReset process.

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Signal

B2BI/ONote










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titleJTAG pins connection

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JTAG Signal

B2B Connector

TMS
TDI
TDO
TCK


JTAG_EN


MIO Pins

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI


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titleMIOs pins

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MIO PinConnected toB2BNotes





































Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test PointSignalB2BNotes
10PWR_PL_OKJ2-120


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titleI2C interface MIOs and pins

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MIO PinSchematicU? PinNotes










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titleI2C Address for RTC

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MIO PinI2C AddressDesignatorNotes





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titleOn-board LEDs

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DesignatorColorConnected toActive LevelNote
















DDR3 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

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titlePower Consumption

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Power Input PinTypical Current
VINTBD*TBD*

* TBD - To Be Determined

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* TBD - To Be Determined

Power Distribution Dependencies

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titlePower Distribution


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Power-On Sequence

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titlePower DistributionSequency


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Power-On Sequence

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titlePower Sequency
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Voltage Monitor Circuit

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titleVoltage Monitor Circuit


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