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Some sources are available: TE0821 Resources

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Template Revision 2.12

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"


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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables

      • Scroll Title
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        Scroll Table Layout
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        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:
        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages
        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview
        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



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-----------------------------------------------------------------------


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Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.


Scroll pdf ignore

Table of Contents

Table of Contents

Overview

The Trenz Electronic TE0821-01-3BI21FA is a powerful 4 x 5 cm MPSoC module with a Xilinx Zynq UltraScale + ZU3EG. In addition, the module is equipped with a 2 GB DDR4 SDRAM chip, 128 MB flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages. Robust high-speed connectors provide a large number of inputs and outputs.

This module is pin compatible with Trenz Electronic TE0820 MPSoC modules (JM2 pin 100 is not connected).

The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.

All components cover at least the industrial temperature range from -40 ° C to + 85 ° C. The temperature range in which the module can be used depends on the customer design and the selected cooling. Please contact us for special solutions.

Refer to http://trenz.org/te0821-info for the current online version of this manual and other available documentation.

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Notes :

Key Features

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups for modules and mainboards:

  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2...ZU5*
    • Engine: CG, EG, EV*
    • Speed: -1LI, -2LE,*, **
    • Temperature: I, E,*, **
  • RAM/Storage
    • Low Power DDR4 on PS
      • Data width: 32bit
      • Size: def. 2GB*
      • Speed:***
    • eMMC
      • Data width: 8Bit
      • size: def. 8GB *
    • QSPI boot Flash in dual parallel mode (size depends on assembly version)
      • Data width: 8bit
      • size: def. 128MB *
    • HyperRAM/Flash (optional, default not assembled)
      • size:*
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • Lattice LCMXO2
    • PLL SI5338
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
  • Interface
    • 132 x HP PL I/Os (3 banks)
    • ETH
    • USB
    • 4 GTR (for USB3, Sata, PCIe, DP)
    • MIO for UART
    • MIO for SD
    • MIO for PJTAG
    • JTAG
    • Ctrl
  • Power
    • 3.3V-5V Main Input
    • 3.3V Controller Input
    • Variable Bank IO Power Input
  • Dimension
    • 4 cm x 5 cm
  • Notes
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination


Key Features'  must be split into 6 main groups for carrier:

  • Modules
    • TE0808, TE807, TE0803,...
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension


  • SoC/FPGA
    • Xilinx Zynq UltraScale+ XCZU3EG-1SFVC784I
      • ZU3EG, 784 Pin Packages
      • Application Processor: Quad-Core ARM Cortex-A53 MPCore
      • Real-Time Processor: Dual-core ARM Cortex-R5 MPCore
      • Graphics Processor: Mali-400 MP2
  • RAM/Storage
    • 2 GByte DDR4 SDRAM, 32-Bit databus-width
    • 128 MByte QSPI boot Flash in dual parallel mode
    • 8 GByte e.MMC Memory (up to 64 GByte)
    • MAC address serial EEPROM with EUI-48 node identity
  • On Board
    • Graphic Processing Unit (GPU) :Mali-400 MP2
  • Interface
    • PCI Express interface version 2.1 compliant
    • SATA 3.1 specification compliant interface
    • DisplayPort source-only interface with video resolution up to 4k x 2k

    • USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
    • 1 GB/s serial GMII interface
    • Hi-speed USB2 ULPI transceiver with full OTG support
    • 34 x High Performance und 96 x High Density PL I/Os
    • 14 x PS MIOs (6 of the MIOs intended for SD card interface in default configuration)
    • 4 x serial PS GTR transceivers
    • Rugged for shock and high vibration
  • Power
    • All power supplies on board
  • Dimension
    • 40 x 50 mm

Block Diagram

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Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .



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titleTE0821 block diagram


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Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .



Scroll Title
anchorFigure_OV_MC
titleTE0821 main components


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  1. Xilinx Zynq UltraScale+ XCZU3EG, U1
  2. Red LED (ERR_OUT), D3
  3. Green LED (ERR_STATUS), D4
  4. Red LED (DONE), D1
  5. GigaBit Ethernet Transceiver, U8
  6. 8Gb DDR4, U2-U3
  7. 512 Mb SPI Flash, U7-U17
  8. Board to Board Connector, JM1
  9. USB2.0 Transceiver,  U18
  10. Board to Board Connector, JM3
  11. Board to Board Connector, JM2
  12. eMMC, U17

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty


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titleInitial delivery state of programmable devices on the module

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Storage device name

Content

Notes

SPI Flash OTP Area

Not programmed

Except serial number programmed by flash vendor.

SPI Flash Quad Enable bit

Programmed

-

SPI Flash main array

Not programmed

-

eFUSE USER

Not programmed

-

eFUSE Security

Not programmed

-
Si5338 OTP NVMNot programmed-
CPLD (LCMXO2-256HC)SC0820-02 QSPI FirmwareSee Boot Process section.


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

Two different firmware versions are available, one with the QSPI boot option and other with the SD Card boot option.

Scroll Title
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titleBoot process.

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MODE Pin

Boot Mode
Low

QSPI

HighSD Card




Scroll Title
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titleReset process.

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Signal

B2BI/ONote










Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

Scroll Title
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titleGeneral PL I/O to B2B connectors information

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FPGA BankB2B ConnectorI/O Signal CountI/O Signal CountVoltage LevelNotes

64

HP

JM2

48

User

Max voltage 1.8V

64

HP

JM2

2

User

Max voltage 1.8V
65

HP

JM2

18

User

Max voltage 1.8V

65

HP

JM3

16

User

Max voltage 1.8V

66

HP

JM1

48

User

Max voltage 1.8V
500MIOJM181.8V-

501

MIO

JM1

6

3.3V

-

505

GTR

JM3

4 lanes

-

-

505

GTR CLK

JM3

1 differential input

-

-



JTAG Interface

JTAG access to the TExxxx SoM through B2B connector JMX.

Scroll Title
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titleJTAG pins connection

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JTAG Signal

B2B Connector

TMSJM2-93
TDIJM2-95
TDOJM2-97
TCKJM2-99 


Pin 89 JTAGEN of B2B connector JM1 is used to control which device is accessible via JTAG. If set to low or grounded, JTAG interface will be routed to the Xilinx Zynq MPSoC. If pulled high, JTAG interface will be routed to the System Controller CPLD.

MIO Pins

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI



Scroll Title
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titleMIOs pins

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MIO PinConnected toB2BNotes





































Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test PointSignalB2BNotes
10PWR_PL_OKJ2-120



Scroll Title
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titleTest Points Information

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Test PointSignalConnected toNotes





































On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


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titleOn board peripherals

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Chip/InterfaceDesignatorNotes
















Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.


Scroll Title
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titleQuad SPI interface MIOs and pins

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MIO PinSchematicU?? PinNotes


























EEPROM

Scroll Title
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titleI2C EEPROM interface MIOs and pins

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MIO PinSchematicU25 PinNotes
MIO39I2C_SDASDA
MIO38I2C_SCLSCL



Scroll Title
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titleI2C address for EEPROM

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MIO PinI2C AddressDesignatorNotes
MIO38...390x50U25


LEDs

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titleOn-board LEDs

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DesignatorColorConnected toActive LevelNote
D1RedDONEHigh
D2GreenERR_STATUSHigh
D3RedERR_OUTHigh


DDR3 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE0821 SoM has 8 Gb volatile DDR4 SDRAM IC for storing user application code and data.

  • Part number: K4A8G165WB-BIRC
  • Supply voltage: 1.2V
  • Speed: 2400 mbps
  • Temperature: -40 ~ 95 °C

Ethernet

Scroll Title
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titleEthernet PHY to Zynq SoC connections

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U?? Pin Signal NameConnected toSignal DescriptionNote







































































Clock Sources

Scroll Title
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titleOsillators

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DesignatorDescriptionFrequencyNote
U11MEMS Oscillator25 MHz
U14MEMS Oscillator25 MHz


Programmable Clock Generator

There is a programmable clock generator on-board (U??) provided in order to generate variable clocks for the module. Programming can be done using I2C via PIN header J??.  The I2C Address is 0x??.

Scroll Title
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titleProgrammable Clock Generator Inputs and Outputs

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U?? Pin
SignalConnected toDirectionNote

IN0





IN1



IN2



IN3



XAXB





SCLK



SDA



OUT0



OUT1



OUT2



OUT3



OUT4



OUT5



OUT6



OUT7



OUT8/OUT9




Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

Scroll Title
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titlePower Consumption

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Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies

Scroll Title
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titlePower Distribution


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Power-On Sequence

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titlePower Sequency


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Voltage Monitor Circuit

Scroll Title
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titleVoltage Monitor Circuit


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Power Rails

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titleModule power rails.

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Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes

























Bank Voltages

Scroll Title
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titleZynq SoC bank voltages.

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Bank          

Schematic Name

Voltage

Notes






























Board to Board Connectors

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  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

    Include Page
    PD:6 x 6 SoM LSHM B2B Connectors
    PD:6 x 6 SoM LSHM B2B Connectors

Include Page
PD:4 x 5 SoM LSHM B2B Connectors
PD:4 x 5 SoM LSHM B2B Connectors


Technical Specifications

Absolute Maximum Ratings

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titlePS absolute maximum ratings

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SymbolsDescriptionMinMaxUnit




V




V











Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Scroll Title
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titleRecommended operating conditions.

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ParameterMinMaxUnitsReference Document



VSee ???? datasheets.



VSee Xilinx ???? datasheet.



°CSee Xilinx ???? datasheet.



°CSee Xilinx ???? datasheet.


Physical Dimensions

  • Module size: 40 mm × 50 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 8 mm.

PCB thickness: 1.74 mm.

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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .



Scroll Title
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titlePhysical Dimension


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Currently Offered Variants 

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Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

    DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


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titleTrenz Electronic Shop Overview

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Trenz shop TE0821 overview page
English pageGerman page


Revision History

Hardware Revision History

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Set correct links to download  arrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

  • Date format:  YYYY-MM-DD


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titleHardware Revision History

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DateRevisionChangesDocumentation Link
2019-04-26REV01
  • Initial Release
REV01


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Scroll Title
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titleBoard hardware revision number.


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Document Change History

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  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


Scroll Title
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titleDocument change history.

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DateRevisionContributorDescription

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
prefixv.
typeFlat
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Page info
infoTypeModified by
typeFlat
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  • Initial Release

--

all

Page info
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typeFlat
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  • --


Disclaimer

Include Page
IN:Legal Notices
IN:Legal Notices