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anchor | Figure_OV_MC |
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title | TE0821 main components |
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draw.io Diagram |
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border | false |
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diagramName | TE0821_OV_MC |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 641 |
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revision | 56 |
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Image Modified |
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- Xilinx Zynq UltraScale+ XCZU3EG, U1
- Red LED (ERR_OUT), D3
- Green LED (ERR_STATUS), D4
- Red LED (DONE), D1
- GigaBit Ethernet Transceiver10/100/1000 Mbps energy efficient ethernet transceiver, U8
- 8Gb DDR4, U2-U3
- 512 Mb SPI FlashMbit QSPI flash memory, U7-U17
- Board to Board ConnectorB2B connector Samtec Razor Beam, JM1
- Programmable clock generator, U10
- USB2.0 Transceiver, U18
- Board to Board ConnectorB2B connector Samtec Razor Beam, JM3Board to Board Connector
- B2B connector Samtec Razor Beam, JM2
- 8 GByte eMMC , U17memory, U6
- Lattice Semiconductor MachXO2 System Controller CPLD, U21
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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Scroll Title |
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anchor | Table_OV_IDS |
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title | Initial delivery state of programmable devices on the module |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Storage device name | Content | Notes |
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SPI QSPI Flash OTP AreaMemory | Not programmed | Except serial number programmed by flash vendor. | SPI Flash Quad Enable bit | Programmed | - | SPI Flash main array | Not programmed | - | eFUSE USER | Not programmed | - | eFUSE Security | Not programmed | - |
| eMMC Memory | Not programmed |
| Programmable Clock GeneratorSi5338 OTP NVM | Not programmed | - |
| CPLD (LCMXO2-256HC) | SC0820-02 QSPI FirmwareSee Boot Process section. |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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Scroll Title |
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anchor | Table_OV_RST |
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title | Reset process. |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Signal | B2B | I/O | Note |
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EN | JM1-28 | Input | CPLD Enable Pin |
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Signals, Interfaces and Pins
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Scroll Title |
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anchor | Table_SIP_B2B |
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title | General PL I/O to B2B connectors information |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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FPGA Bank | Type | B2B Connector | I/O Signal Count |
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I/O Signal Count | 64HP48 | User24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 25 | HD | JM1 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 26 | HD | JM1 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage | 18V64HP2 | 24x I/O, 12x LVDS Pairs | Variable | User 18V18 | 18x I/O, 9x LVDS Pairs | Variable | User16 | 16x I/O, 8x LVDS Pairs | Variable | User | Max voltage 1.8V | 66 | HP | JM1 | 48 | User500MIOJM1 | 8 | 1.8V | - | JM3 | 16x I/O, 8x LVDS Pairs | - | 4x lanes |
501 | MIO | JM1 | 6 | 3.3V | -4 lanes-505GTR CLK | JM3 | 1 differential input | - | -
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JTAG Interface
JTAG access to the TExxxx SoM through B2B connector JMX.
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