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Scroll Title
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titleGeneral PL I/O to B2B connectors information

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FPGA BankTypeB2B ConnectorI/O Signal CountVoltage LevelNotes
24HDJM224x I/O, 12x  LVDS PairsVariable Max voltage 3.3V
25HDJM124x I/O, 12x  LVDS PairsVariable Max voltage 3.3V
26HDJM124x I/O, 12x  LVDS PairsVariable Max voltage 3.3V
44HDJM224x I/O, 12x  LVDS PairsVariableMax voltage 3.3V
65

HP

JM2

18x I/O, 9x LVDS Pairs

VariableMax voltage 1.8V

65

HP

JM3

16x I/O, 8x LVDS Pairs

Variable

Max voltage 1.8V

66

HP

JM1

48

Variable

Max voltage 1.8V
505GTRJM316x I/O, 8x LVDS Pairs-4x lanes
505GTR CLKJM31x Diff Clock-

501

MIO

JM1

15 I/O

3.3V




JTAG Interface

JTAG access to the TExxxx SoM Xilinx Zynq UltraScale+ is applicable by using Lattice MachXO CPLD  through B2B connector JMXJM2.

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titleJTAG pins connection

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JTAG Signal

B2B Connector

Note
TMSJM2-93
TDIJM2-95
TDOJM2-97
TCKJM2-99 

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JTAGEN

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JM1-89Pulled Low: Xilinx Zynq UltraScale+ MPSoC
Pulled High: Lattice MachXO CPLD


MGT Lanes

There are 4x MGT Lanes connected to FPGA Bank 505-GTR.

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titleMGT Lanes connection

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Lane

SchematicB2BNote
0
  • B505_RX0_P
  • B505_RX0_N
  • B505_TX0_P
  • B505_TX0_N
  • JM3-26
  • JM3-28
  • JM3-25
  • JM3-27

1
  • B505_RX1_P
  • B505_RX1_N
  • B505_TX1_P
  • B505_TX1_N
  • JM3-20
  • JM3-22
  • JM3-19
  • JM3-21

2
  • B505_RX2_P
  • B505_RX2_N
  • B505_TX2_P
  • B505_TX2_N
  • JM3-14
  • JM3-16
  • JM3-13
  • JM3-15

3
  • B505_RX2_P
  • B505_RX2_N
  • B505_TX2_P
  • B505_TX2_N
  • JM3-8
  • JM3-10
  • JM3-7
  • JM3-9


MIO Pins

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI



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titleMIOs pins

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MIO PinConnected toB2BNotes
0...5QSPI Flash, U7-SPI Flash
7...12QSPI Flash, U17-SPI Flash
13...23eMMC, U6

24ETH Transceiver, U8-ETH_RST
25USB2.0 Transceiver, U18-OTG_RST
26...33User MIOJM1
34...37N.C-N.C
38...39EEPROM, U25-I2C_SDA/SCL
40...45N.C
N.C
46...51SD CardJM1
52...63USB2.0 Transceiver, U18-
63...77Ethernet Transceiver, U8-


Test Points

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hiddentrue
idComments

you must fill the table below with group of MIOs Test Point which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematicindicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test PointSignalMIO PinConnected toB2BNotes
10PWR_PL_OKJ2-120MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI



Scroll Title
anchorTable_SIP_MIOsTPs
titleMIOs pinsTest Points Information

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MIO PinConnected toB2BNotes

Test Points

you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Notes

Test PointSignalConnected toNotes
1I2C_SCLEEPROM, U25
2I2C_SDAEEPROM, U25
3SRST_BFPGA Bank 503PSCONFIG
4PS_CLKFPGA Bank 503PSCONFIG
5PROG_BFPGA Bank 503PSCONFIG
6INIT_BFPGA Bank 503PSCONFIG
7DONERed LED, D1
8PS_LP0V85Voltage Regulator, U12
9DDR_2V5Voltage Regulator, U4
10PS_AVCCVoltage Regulator, U9
11DDR_1V2Voltage Regulator, U15
12PS_AVTTVoltage Regulator, U3
13PS_FP0V85Voltage Regulator, U26
14POR_BVoltage Translator, U19
15PS_PLLVoltage Regulator, U23
16PL_VCCINTVoltage Regulator, U5
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Test PointSignalB2BNotes
10PWR_PL_OKJ2-120
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titleTest Points Information
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Test PointSignalConnected to


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

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Scroll Title
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titleOn board peripherals

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Chip/InterfaceDesignatorNotes
QSPI FlashU7, U17
EEPROMU25
DDR4 SDRAMU2,U3
OscillatorsU32, U14, U12
CPLDU21
LEDsD1...3


Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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