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Bank Voltages

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anchor	Table_PWR_BV
title	Zynq SoC bank voltages.

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Bank          

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Voltage

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id	Comments

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VIN 1, 3, 5 2, 4, 6, 8 Input Supply voltage from the carrier board 3.3V - 10, 12 Output Internal 3.3V voltage level 3.3VIN 13, 15 - Input Supply voltage from the carrier board 1.8V 39 - Output Internal 1.8V voltage level JTAG VREF - 91 Output JTAG reference voltage. Attention: Net name on schematic is "3.3VIN" VCCO_64 - 7, 9 Input High performance I/O bank voltage VCCO_65 - 5 Input High performance I/O bank voltage VCCO_66 9, 11 - Input High performance I/O bank voltage

Bank Voltages

Scroll Title
anchor Table_PWR_BV title Zynq SoC bank voltages.
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Bank           Schematic Name Voltage Notes

Board to Board Connectors

Page properties
hidden true id Comments
This section is optional and only for modules. use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors Include Page PD:6 x 6 SoM LSHM B2B Connectors PD:6 x 6 SoM LSHM B2B Connectors

Include Page
PD:4 x 5 SoM LSHM B2B Connectors PD:4 x 5 SoM LSHM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

Scroll Title
anchor Table_TS_AMR title PS absolute maximum ratings
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Description Min Max Unit Notes VIN supply voltage -0.3 7 V See EN6347QI and TPS82085SIL datasheets 3.3VIN supply voltage -0.1 3.630 V Xilinx DS925 and TPS27082L datasheet PS I/O supply voltage, VCCO_PSIO -0.5 3.630 V Xilinx document DS925 PS I/O input voltage -0.5 VCCO_PSIO + 0.55 V Xilinx document DS925 HP I/O bank supply voltage, VCCO -0.5 2.0 V Xilinx document DS925 HP I/O bank input voltage -0.55 VCCO + 0.55 V Xilinx document DS925 PS GTR reference clocks absolute input voltage -0.5 1.1 V Xilinx document DS925 PS GTR absolute input voltage -0.5 1.1 V Xilinx document DS925 Voltage on SC CPLD pins -0.5 3.75 V Lattice Semiconductor MachXO2 datasheet Storage temperature -40 +85 °C See eMMC datasheet

use "include page" macro and link to the general B2B connector page of the module series,

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Technical Specifications

Absolute Maximum Ratings

V

Scroll Title
anchor Table_TS_AMR title PS absolute maximum ratings
Scroll Table Layout
orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style	widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true
Symbols	Description	Min	Max	Unit
V