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On-board Gigabit Ethernet PHY (U8) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.000000 MHz oscillator (U21U11).

High-speed USB ULPI PHY

Hi-speed USB ULPI PHY (U32U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO52..63, bank 502. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U33U14).

MAC Address EEPROM

A Microchip 24AA025E48 serial EEPROM (U25) contains a globally unique 48-bit node address, which is compatible with EUI-48(TM) specification. The device is organized as two blocks of 128 x 8-bit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. It is accessible over I2C bus with slave device address 0x50.

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Clock SourceSchematic NameFrequencyClock Destination
SiTime SiT8008BI oscillator, U21U32PS_CLK33.333333 MHzZynq MPSoC U1,pin R16
SiTime SiT8008BI oscillator, U21U11-25.000000 MHzQuad PLL clock generator U10, pin 3, and Ethernet  PHY U8, pin 34
SiT8008AI-73-XXS oscillator, U14-52.000000  MHzUSB PHY U18, Pin 26

Table 13: Reference clock signals

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  • Corrected PLL section
  • CorrectedDesignators USB, ETH PHY, CLK section
2020-02-03v.85Martin Rohrmüller
  • Corrected #MIOs for QSPI and USB in block diagram
2019-11-28v.81Martin Rohrmüller
  • typo and designator in section USB interface corrected
2019-10-30v.80John Hartfiel
  • typo correction
2019-09-17v79Martin Rohrmüller
  • Updated according to PCN-20190110: eMMC, QSPI-Flash

2019-07-17

v.78Martin Rohrmüller
  • Corrected PJTAG Mio Pin29 in table 8

2019-05-08

v.77John Hartfiel
  • Corrected EEPROM I2C Address
  • Correction USB PHY connection

2018-11-12

v.74

John Hartfiel
  • update boot section

2018-08-30

v.73John Hartfiel
  • typo correction
  • update CPLD section
  • add LEDs to component list
  • add 3D picture of REV03 instead of REV01 picture

2018-07-12

v.69Ali Naseri
  • Update PCB Rev03

2018-06-11

v.61John Hartfiel
  • Rework chapter currently available products
  • add PJTAG note to MIOtable
2018-03-12v.54
  • Correction Power Rail Section
2017-11-20v.51John Hartfiel
  • Correction Default MIO Configuration Table
2017-11-10v.50John Hartfiel
  • Replace B2B connector section
2017-10-18v.49John Hartfiel
  • add eMMC section
2017-09-25v.48John Hartfiel
  • Correction in the "Board to Board (B2B) I/Os" section
  • Update in the "Variants Currently In Production" section
2017-09-18v.47John Hartfiel
  • Update PS MIO table
2017-08-30v.46Jan Kumann
  • MGT lanes section added.

2017-08-24

v.36

John Hartfiel
  • Correction in the  "Key Features" section.
2017-08-21v.34John Hartfiel
  • "Initial delivery state" section updated.
2017-08-21v.33Jan Kumann
  • HW revision 02 block diagram added.
  • Power distribution and power-on sequence diagram added.
  • System Controller CPLD and DDR4 SDRAM sections added.
  • TRM update to the template revision 1.6
  • Weight section removed.
  • Few minor corrections.



2017-08-18


v.7

John Hartfiel
  • Style changes
  • Updated "Boot Mode", "HW Revision History", "Variants Currently In Production" sections
  • Correction of MIO SD Pin-out, System Controller chapter
  • Update and new sub-sections on "On Board Peripherals and Interfaces" sections

2017-08-07

v.5

Jan Kumann

  • Initial version
--all

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