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| Scroll Title |
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| anchor | Figure_OV_BD |
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| title | TE0821 block diagram |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| |
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| diagramName | TE0821_OV_BD |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| diagramDisplayName | |
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| lbox | true |
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| diagramWidth | 641 |
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| revision | 45 |
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| Scroll Only |
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Main Components
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Quad SPI Flash Memory
| Page properties |
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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| Scroll Title |
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| anchor | Table_OBP_SPI |
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| title | Quad SPI interface MIOs and pins |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Pin | Schematic | Notes |
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| U7 Pin | U17 Pin |
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| nCS | MIO5 | MIO7 |
| | CLK | MIO0 | MIO12 |
| | DI/IO0 | MIO4 | MIO8 |
| | DO/IO1 | MIO1 | MIO9 |
| | nHOLD/IO3 | MIO3 | MIO11 |
| | WP/IO2 | MIO2 | MIO10 |
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EEPROM
There is a 2Kb EEPROM provided on the module TE0821.
| Scroll Title |
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| anchor | Table_OBP_EEP |
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| title | I2C EEPROM interface MIOs and pins |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Schematic | U25 Pin | Notes |
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| MIO39 | I2C_SDA | SDA |
| | MIO38 | I2C_SCL | SCL |
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| Scroll Title |
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| anchor | Table_OBP_LED |
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| title | On-board LEDs |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
|---|
| style | |
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| widths | |
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| sortByColumn | 1 |
|---|
| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Color | Connected to | Active Level | Note |
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| D1 | Red | DONE | HighLow |
| | D2 | Green | ERRUSR_STATUSLED | High |
| | D3 | Red | ERR_OUT | High |
| | D4 | Green | ERR_STATUS | High |
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DDR4 SDRAM
| Page properties |
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
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| Scroll Title |
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| anchor | Table_OBP_ETH |
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| title | Ethernet PHY to Zynq SoC connections |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Pin | Schematic | Connected to | Note |
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| MDIP0...3 | PHY_MDI0...3 | B2B, JM1 |
| | MDC | ETH_MDC | MIO76 |
| | MDIO | ETH_MDIO | MIO77 |
| | S_IN | S_IN | B2B, JM3 |
| | S_OUT | S_OUT | B2B, JM3 |
| | TXD0..3 | ETH_TXD0...3 | MIO65...68 |
| | TX_CTRL | ETH_TXCTL | MIO69 |
| | TX_CLK | ETH_TXCK | MIO64 |
| | RXD0...3 | ETH_RXD0...3 | MIO71...74 |
| | RX_CTRL | ETH_RXCTL | MIO75 |
| | RX_CLK | ETH_RXCK | MIO70 |
| | LED0...2 | PHY_LED0...2 | FPGA Bank 66 |
| | RESETn | ETH_RST | MIO24 |
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Clock Sources
| Scroll Title |
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| anchor | Table_OBP_CLK |
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| title | Osillators |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Description | Frequency | Note |
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| U11 | MEMS Oscillator | 25 MHz |
| | U14 | MEMS Oscillator | 52 MHz |
| | U32 | MEMS Oscillator | 80 MHz |
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|
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There is a programmable clock generator on-board (U??U10) provided in order to generate variable clocks for the module. Programming can be done using I2C via PIN header J??. The I2C Address is 0x??0x70 or 0x71.
| Scroll Title |
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| anchor | Table_OBP_PCLK |
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| title | Programmable Clock Generator Inputs and Outputs |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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U?? U25 Pin
| Signal | Connected to | Direction | Note |
|---|
IN0 | IN1 | IN2 | IN3 | XAXB | SCLK | SDA | ..1 | CLK_IN | JM3 | IN |
| | IN2 | CLK_25M | Oscillator, U11 | IN |
| | SCL | I2C_SCL | EEPROM,U25 | INOUT |
| | SDA | I2C_SDA | EEPROM,U25 | INOUT |
| | CLK0 | CLK0 | JM3 | OUT |
| | CLK1 | B505_CLK3 | FPGA Bank 505 | IN |
| | CLK2 | B505_CLK1 | FPGA Bank 505 | IN |
| | CLK3 | CLK3_N |
| IN | OUT0 | OUT1 | OUT2 | OUT3 | OUT4 | OUT5 | OUT6 | OUT7 | OUT8/OUT9 |
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Power and Power-On Sequence
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| Scroll Title |
|---|
| anchor | Table_PWR_BV |
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| title | Zynq SoC bank voltages. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic Name | | Notes |
|---|
| 64 HP | VCCO_64 | User | HP: 1.0V to 1.8V | | 65 HP | VCCO_65 | User | HP: 1.0V to 1.8V | | 66 HP | VCCO_66 | User | HP: 1.0V to 1.8V | | 500 PSMIO | VCCO_PSIO0_500 | 1.8V | - | | 501 PSMIO | VCCO_PSIO1_501 | 3.3V | - | | 502 PSMIO | VCCO_PSIO2_502 | 1.8V | - | | 503 PSCONFIG | VCCO_PSIO3_503 | 1.8V | - | | 504 PSDDR | VCCO_PSDDR_504 | 1.2V | - |
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Board to Board Connectors
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