• Last modified: Oct 14, 2025

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Overview

The Trenz Electronic TEB0835 is a baseboard in PCIe card form factor for a TE0835 module which is based on AMD UltraScale+ RF-SoC. The baseboard is equipped with a micro SD card reader, micro USB 2.0, 8x SMP connectors for ADC inputs and 8x SMP connectors for DAC outputs, 2x UMCC connectors for clock signal inputs, 4x green status LEDs, 5x green User LEDs, reset push button, DIP switches for configuration, a FT2232H FTDI based SoM programmer, a programmable clock generator and a temperature sensor. 

Refer to http://trenz.org/teb0835-info for the current online version of this manual and other available documentation.

Key Features

  • On Board

    • Programmable Clock Generator

    • USB-to-JTAG/UART FTDI bridge

    • Oscillator
    • Battery Holder for CR1220
    • Temperatur Sensor
    • 5x green user LEDs
    • 4x green status LEDs

  • Interface

    • Trenz 6.5 x 9 SoM socket: 2x B2B (Samtec SS5) Connector
    • High speed coaxial connectors:
      • 8x ADC SMP
      • 8x DAC SMP
      • 2x CLK U.FL/UMCC
      • CLK SMA
      • 9x CLK U.FL 1)
    • PCIe x4 (mechanical PCIe x8)
    • 2x PCUO FireFly™
    • RJ45 GbE connector
    • Micro USB 2.0 for SoM connection
    • Micro USB 2.0 for JTAG and UART connection (FTDI FT2232H)
    • Micro SD Card connector
    • 2x pin header
    • 4-bit DIP switch
    • 2x 2-bit DIP switch
    • Reset button

  • Power

    • 12 V power supply via PCIe power header OR PCIe x8 slot

  • Dimension

    • 106.65 mm x 167.65 mm

  • Notes
    1) Assembly option dependent.

Block Diagram

TEB0835 block diagram

Main Components

TEB0835 main components
  1. Clock Generator, U5
  2. Crystal, Y1 - 54 MHz
  3. Oszillator, U6 - 100 MHz
  4. FireFly resistor detect network
  5. FireFly load switch, Q2
  6. I2C Multiplexer, U7
  7. SDIO level shifter, U11
  8. SD Card voltage switch, Q1
  9. USB to JTAG/UART FTDI, U12
  10. Oscillator, U16 - 12 MHz
  11. USB VBUS Power Switch, U17
  12. Voltage protection, U2, U3
  13. Temperature sensor, U9
  14. Power good LED, D1, D2, D3
  15. LED, LED5
  16. User LED, LED 4
  17. User LED, LED0, LED1, LED2, LED3
  18. Light Pipe, LP1
  19. ADC/DAC SMP, XS1 ... XS16
  20. U.FL/UMCC, J37
  21. U.FL/UMCC, J20, J27, J32, J33, J34, J35, J38, J42, J43
  22. SMA, J36
  23. SMA, J46
  24. B2B Connector, JB1, JB2
  25. Reset button, BTN1
  26. DIP switch, SW1
  27. DIP switch, SW2
  28. DIP switch, SW3
  29. DIP switch, S1
  30. DIP switch, S2
  31. DIP switch, S7
  32. CR1220 battery holder, B1
  33. FireFly 0, J22, J25
  34. FireFly 1, J23, J24
  35. 4-bit Pin Header, J21
  36. 6-bit Pin Header, J40
  37. 3-bit Pin Header, J41
  38. PCIe Power Header, J19
  39. PCIe Slot, J26
  40. MicroSD Card Slot, J28
  41. Micro USB Connector, J29
  42. Micro USB Connector, J30
  43. RJ45 connector, J31
  44. 2x 20 pin IO Connector, J44
  45. 2x 20 pin IO Connector, J45

Initial Delivery State

Storage device name

Content

Notes

EEPROM, U15

AMD programmer license

Do not overwrite!

Programmable Clock Generator, U5

Not programmed


Initial delivery state of programmable devices on the module

Signals, Interfaces and Pins

Connectors

Connector Type

Designator

Interface

IO CNT

Notes

SMP

XS1 ... XS8

ADC

8x SE


SMP

XS9 ... XS16

DAC

8x SE


SMA

J36 / J46

CLK

2x SE


U.FL/UMCC

J37

CLK

1x SE


U.FL/UMCC

J20 / J27 / J32 / ... / J35 / J38 / J42 / J43

CLK

9x SE

Not assembled.

B2B

JB1

PCIe

4x DIFF


B2B

JB1

FireFly

8x DIFF


B2B

JB1

USB

1x DIFF


B2B

JB1

ETH / MDI

4x DIFF


B2B

JB1

ETH / LED

3x SE


B2B

JB1

CLK

2x DIFF


B2B

JB1

CLK

1x DIFF


B2B

JB1

SD

7x SE


B2B

JB1

MIO

19x SE


B2B

JB1

JTAG

4x SE


B2B

JB1

CPLD IO

4x SE


B2B

JB1

I2C

3x SE


B2B

JB1

UART

2x SE


B2B

JB2

ADC

8x DIFF


B2B

JB2

ADC CLK

4x DIFF


B2B

JB2

ADC BIAS

8x SE


B2B

JB2

DAC

8x DIFF


B2B

JB2

DAC CLK

2x DIFF


B2B

JB2

CLK

5x DIFF


B2B

JB2

IO

14x SE


B2B

JB2

IO

24x SE / 12x DIFF


PCIe x4

J26

PCIe

8x DIFF


PCIe x4

J26

PCIe CLK

1x DIFF


Micro USB

J29

USB

1x DIFF

FTDI bridge

Micro USB

J30

USB

1x DIFF


Pin Header

J40

JTAG

4x SE


RJ45 Ethernet

J31

ETH / MDI

8x SE / 4x DIFF


FireFly 0

J22 / J25

PCIe

4 x MGT


FireFly 1

J24 / J23

PCIe

4x MGT


har-flex connector

J44

MIO

19x SE


har-flex connector

J44

UART

2x SE


Pin Header

J41

I2C 1.8 V

3x SE


har-flex connector

J44

I2C 1.8 V

3x SE


har-flex connector

J45

IO

22x SE / 11x DIFF


har-flex connector

J45

CLK

2x SE / 1x DIFF


Pin Header

J21

FAN

3x SE


Board Connectors


Test Points



REV03REV02

REV01

Test Point

Top

Bottom

Notes

Signal

- = Test Point not used
Designator and/or only net name

TP1


x


V_MODULE

5V

5V

TP2


x


GND

GND

GND

TP3

x



GND

GND

GND

TP4

x



ADC0_VCM

ADC0_VCM

ADC0_VCM

TP5

x



ADC1_VCM

ADC1_VCM

ADC1_VCM

TP6


x


5V_VBUS

USB_VBUS

USB_VBUS

TP7

x



FT_B_TX

FT_B_TX

FT_B_TX

TP8

x



FT_B_RX

FT_B_RX

FT_B_RX

TP9

x



ADC2_VCM

ADC2_VCM

ADC2_VCM

TP10

x



ADC3_VCM

ADC3_VCM

ADC3_VCM

TP11

x



ADC4_VCM

ADC4_VCM

ADC4_VCM

TP12

x



ADC5_VCM

ADC5_VCM

ADC5_VCM

TP13

x



ADC6_VCM

ADC6_VCM

ADC6_VCM

TP14

x



ADC7_VCM

ADC7_VCM

ADC7_VCM

TP15


x


PSBATT

PSBATT

-

TP16


x


CLKE_P

CLKE_P

-

TP17


x


CLKE_N

CLKE_N

-

TP18


x


CLKF_P

CLKF_P

-

TP19


x


CLKF_N

CLKF_N

-

TP20


x


CLKD_P

CLKD_P

-

TP21


x


CLKD_N

CLKD_N

-

TP22

x



1.8V

-

-

TP23


x


1.8V

-

-

TP24


x


12V

-

-

TP25

x



12V

-

-

TP26

x



3.3V

-

-

TP27


x


3.3V

-

-

TP28

x



PG_5V

-

-

TP29


x


PG_5V

-

-

TP30

x



3.3V

-

-

TP31


x


3.3V

-

-

TP32


x


FF0_VCC

-

-

TP33

x



V_MODULE

-

-

TP34


x


3.3V_FTDI

-

-

TP45


x


FF1_VCC

-

-

Test Points Information

On-board Peripherals

Chip/Interface

Designator

Connected To

Notes

Clock Generator

U5
  • Crystal, Y1
  • Oscillator, U6
  • B2B, JB1, JB2
  • SMA, J36
  • U.FL, J37

SDIO Level Shifter

U11
  • SD Card Socket, J28
  • B2B, JB1

FTDI

U12
  • EEPROM, U15
  • Oscillator, U16
  • Level Shifter, U13, U14
  • Micro USB, J29

EEPROM

U15
  • FTDI, U12

Contains AMD programmer license.

Do not overwrite!

I2C Multiplexer

U7
  • Temperature Sensor, U9
  • B2B, JB1
  • FireFly 0, J22, J25
  • FireFly 1, J23, J24

DCDC

U8
  • Temperature Sensor, U9
  • B2B, JB1

Fan controller

U9
  • DCDC, U8
  • FAN Connector, J21

Crystal

Y1
  • Clock Generator, U5
54 MHz
OscillatorU6
  • Clock Generator, U5
100 MHz

Oscillator

U16
  • FTDI, U12
12 MHz
On board peripherals

Configuration and System Control Signals

Signal Name

Connector.Pin

Direction1)

Description

RESETN

BTN1

IN

SoM reset signal.

RESETN

JB1.36

OUT

SoM reset signal.

CPLD_IO0 / CPLD_IO1 /

CPLD_IO2

S1A / S1B / S1C

IN

System Controller configurations

signals. SoM Firmware dependent.

CPLD_IO0 / CPLD_IO1 /

CPLD_IO2

JB1.26 / JB1.28 / JB1.32

OUT

System Controller configurations

signals. SoM Firmware dependent.

MODULE_PG

JB1.34

IN

SoM power good signal.

VBATT

B1

IN

CR1220 Backup Battery power supply.

DCDCEN

SW1.2

IN

DCDC U4 enable source selection.

MODE_5V

SW2.2

IN

DCDC U8 mode selection.

EN_5V

SW3.2

IN

DCDC U8 disable option.

FAN_PWR / FAN_TACH /

FAN_PWM

J21.2 / J21.3 / J21.4

Signal

dependent

Fan connection.

PCIE_PRSNTb

J26.A1 / J26.B48

IN

PCIe present handling.

PCIE_RSTb_R

J26.A11

IN

PCIe reset signal.

PCIe_RESET_N

JB1.48

OUT

PCIe reset signal

DSPLL0_SEL0 / DSPLL0_SEL1

S2A / S2B

IN

Clock generator input source selection.

FF1_CPRSNT# / FF0_CPRSNT#

S7A / S7B

IN

FireFly Host/Target selection.

UART0_RX / UART0_TX

JB1.43 / JB1.45

Signal

dependent

UART

UART0_RX / UART0_TX

J44.A4 / J44.A3

Signal

dependent

UART

CPLD_JTAGEN

S1D

IN

JTAG target selection.

CPLD_JTAGEN

JB1.30

OUT

JTAG target selection. SoM dependent.

JTAG_TDO / JTAG_TDI /

JTAG_TCK / JTAG_TMS

JB1.18 / JB1.20 /

JB1.22 / JB1.24

Signal

dependent

JTAG.

JTAG_TMS / JTAG_TDI /

JTAG_TDO / JTAG_TCK

J40.1 / J40.2 /

J40.3 / J40.4

Signal

dependent

JTAG.
DSPLL0_SCL / DSPLL0_SDA

J41.1 / J41.3

Signal

dependent

1.8 V Clock generator configuration I2C interface.

I2C0_INTR_N / I2C0_1V8_SDA /

I2C0_1V8_SCL

J44.A16 / J44.A17 / J44.A18 

Signal

dependent

1.8 V SoM I2C interface.

I2C0_1V8_SCL/I2C0_1V8_SDA /

I2C0_INTR_N

JB1.11 / JB1.13 / JB1.15

Signal

dependent

1.8 V SoM I2C interface.

1) Direction:

    • IN: Input from the point of view of this board.

    • OUT: Output from the point of view of this board.

    • INOUT: Bidrectional signal.
Controller signal.

Power and Power-On Sequence

Power Rails

Power Rail Name / Schematic Name

Connector.Pin

Direction1)

Notes

12V_input_A

J19.1 / J19.2 / J19.3

IN

Baseboard power supply.

Main power supply priority.

12V_input_B

J26.A2 / J26.A3 / J26.B1 / J26.B2 / J26.B3

IN

Baseboard power supply.

Secondary power supply priority.

V_MODULE

JB1.1 / JB1.2 / JB1.3 / JB1.4 / JB1.5 / JB1.6 / JB1.8

OUT

SoM power supply.

Variant "-A": 5 V

Variant "-B": 12 V

PSBATT

JB1.14

OUT

CR1220 backup battery power supply.

3.3V_MODULE

JB1.16

IN

Baseboard periphery power supply by SoM.

1) Direction:

    • IN: Input from the point of view of this board.

    • OUT: Output from the point of view of this board.

Module power rails.

Recommended Power up Sequencing


Sequence

Net name

Recommended Voltage Range

Pull-up/down

Description

Notes

----Configuration signal setup.See Configuration and System Control Signals.
112V_input_A / 12V_input_B12 V (± 10 %)-Main Power supply.

Carrier power supply. Power consumption depends mainly on design and cooling solution.

2

Switch SW1 depending setting: 2a or 2b

2a

PG_5V

↔

 DCDC_EN

5 V (± 5 %)

(PG_5V

↔

V_5V0)


-

Baseboard power rails 3.3 V and 1.8 V are enabled via baseboard 5 V DCDC (U8) regulator independent of SoM.


2b


MODULE_PG

↔

DCDC_EN

SoM

dependent.


-SoM enables baseboard power rails 3.3 V and 1.8 V via signal "MODULE_PG".


Optional periphery usage:

USBUSB0_CPEN5 V (± 5 % )-Handled via SoM.


FireFlyFF_PWR_EN1.8 V (± 5 %)-

Handled via SoM.


Baseboard Design Hints

Board to Board Connectors

The module has two 160-pin double-row REF-192552-02 connector on the bottom side. The counterpart REF-192552-01 is placed on the Baseboard.

Order
number

REF NumberSamtec NumberTypeMated HeightData sheetComment
27220REF-192552-02ST5-80-1.50-L-D-P-TRModule connector5 mmhttp://suddendocs.samtec.com/catalog_english/st5.pdfStandard connector
used on module
27219REF-192552-01SS5-80-3.50-L-D-K-TRBaseboard connector5 mmhttp://suddendocs.samtec.com/catalog_english/ss5.pdfStandard connector
used on board
Connectors.

 With different connectors from the used series other mating heights are possible (according to the Datasheet). The module and base board can be manufactured using other connectors upon request.

Connector SpecificationsValue
Insulator materialLiquid crystal polymer
Stacking height5 mm
Contact materialPhosphor-bronze
PlatingAu or Sn over 50 μ" (1.27 μm) Ni
Current rating1.6 A per pin (2 pins powered)
Operating temperature range-55 °C to +125 °C
RoHS compliantYes
Connector specifications.
Connector Speed Ratings

The LSHM connector speed rating depends on the stacking height; please see the following table:

Stacking heightSpeed rating
5 mm, Single-Ended 13.5GHz /  27Gbps
5 mm, Differential 20GHz / 40Gbps
4 mm, Single-Ended 13GHz /  26Gbps
4 mm, Differential 13.5GHz / 27Gbps
Speed rating.
Current Rating

Current rating of  Samtec Razor Beam™ SS5/ST5 B2B connectors is 1.6A per pin (2 pins powered).

Connector Mechanical Ratings
  • Shock: 100G, 6 ms sawtooth wave
  • Vibration: 7.56G 'RMS', 2 hours per axis, 3 axes total
Manufacturer Documentation

  File Modified
PDF File hsc-report-sma_st5-ss5-04mm_web.pdf May 05, 2020 by Pedram Babakhani
PDF File hsc-report-sma_st5-ss5-05mm_web.pdf May 05, 2020 by Pedram Babakhani
PDF File ss5_catalog.pdf May 05, 2020 by Pedram Babakhani
PDF File ss5-st5_specs.pdf May 05, 2020 by Pedram Babakhani



Technical Specifications

This TRM is generic for all variants.

  • The voltage ranges are generally the same across variants, but exceptions are possible. Output voltage rail "V_MODULE" differs between variants "-A" and "-B".
  • The temperature range can differ depending on the assembly version.
  • The combination of a carrier and a SoM might have different requirements.

Variants of modules are described here: Article Number Information. Please contact us to inquire options.

Absolute Maximum Ratings *)

Power Rail Name/ Schematic Name

Description

Min

Max

Unit

12V_input_A

Baseboard power supply.

Main power supply priority.

0

60

V

12V_input_B

Baseboard power supply.

Secondary power supply priority.

0

60

V

Absolute maximum ratings

*) Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Condition". Exposure to absolute-maximum rated conditions for extended periods may affect device reliability.

Recommended Operating Conditions

Temperature range

Trenz Electronic classifies modules into temperature range categories by subsumption of its component data (PCB, ICs, connectors, passive components). The temperature ranges are values for ambient air temperature and do not reflect the junction temperature of individual components.

The categories are:

    Modules with commercial (C) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 70 °C.
    Modules with extended (E) temperature grade are equipped with components that cover at least the ambient temperature range of 0 °C to 85 °C.
    Modules with industrial (I) temperature grade are equipped with components that cover at least the ambient temperature range of -40 °C to 85 °C.

These categories do not take into account the entire custom system consisting of:

    Customer SoC design. The allowed main SoC temperature range is specified from the vendor by junction temperature using corresponding classes (C, E, I). See vendor documentation.
    Cooling solution, active and or passive cooling.
    Climate or environmental conditions besides ambient temperature range.
    Module orientation, neighbouring assemblies, neither other heat sources nor the SoC as heat source to other components.

Classification of the module can be locked up here: Article Number Information i.e.: TExxxx-xx-xx'I'xx, the 'I' indicates that all components are at least in Industrial temperature class.

The temperature of individual components should not exceed the specified range due to self-heating or heating by adjacent components. The actual operating temperature range will depend on the customer design, usage, environment and cooling solution. Consult Cooling Solutions for more information.

Voltage rails

The following table aims to be generic for all variants. The voltage ranges are consistend across assembly variants, but exceptions are possible (custom request).

Parameter

Min

Max

Unit

Reference Document

12V_input_A

10.813.2

V


12V_input_B

10.813.2

V


Recommended operating conditions.

Physical Dimensions

  • Module size: 106.6  x 167.6 mm. Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 5 mm.

  • PCB thickness: 1.564 mm ± 10 %.

All dimensions are shown in millimeters.

Physical Dimension

Currently Offered Variants 

Trenz shop TEB0835 overview page

English page

German page

Trenz Electronic Shop Overview

Revision History

Hardware Revision History

The hardware revision number is located on the PCB next to the module identifier, separated by a dash.

Board hardware revision number.


Date

Revision

Changes

Documentation Link

2024-12REV03
  1. Changed DCDC (U1, U4) from TPS82085SIL to TPS62913RPUR, changed input power supply from voltage rail "5V" to "12V" and adapted circuit accordingly. Added switch (SW1) for DCDC (U4) enable signal.
  2. Changed load switch TPS27081ADDCR (Q1) to MP5077GG-Z and adapted circuit.
  3. Changed battery supply circuit.
    1. Changed output voltage for net "PSBATT" from 1.8 V to 1.2 V.
    2. Changed placement order for battery holder (B1), diode (D13) and LDO (U18).
    3. Changed LDO (U18) from TPS780180300DRV to TPS7A0212PDBVR.
    4. Changed diode (D13) from SDMG0340LC-7-F to BAS70-05W.
    5. Changed capacitor (C86) from 4.7 μF to 470 nF.
  4. Added optional not assembled DCDC (U8) enable switch (SW3, R271).
  5. Added optional not assembled DCDC (U8) mode selection switch (SW2, R272).
  6. Changed 10 nF capacitor (C37, C40) to 1 nF to adjust inrush current.
  7. Renamed module power rail "5V" to "V_MODULE".
  8. Added assembly option to supply power net "V_MODULE either from power net "V_5V0" via ferrite bead (L36, L37) (default) or from power net "12V" via ferrite bead (L38, L39) (assembly option). Added capacitor (C202 ... 207).

  9. Changed LED connection architecture.

    1. Connected B2B connector signal (J18 [REV02] / JB2 [REV03]) signal ([Pin - Signal name], [122 - B49_L5_P], [124 - B49_L5_N], [126 - B49_L6_P], [128 - B49_L6_N]) to connector J45.

    2. Connected B2B connector signal (J18 [REV02] / JB2 [REV03]) signal ([Pin - Signal name], [122 - B49_L5_P], [124 - B49_L5_N], [126 - B49_L6_P], [128 - B49_L6_N], [130 - B49_L7_P]) via 33 Ohm resistor to added MOSFET (T2, T37, T38) [REV03] switching LEDs.

    3. Changed LED designator (D6 → LED0, D7 → LED1, D8 → LED2, D9 → LED3, D10 → LED4, D12 → LED5).

    4. Removed LED (D11).

    5. Changed 330 Ohm resistor (R216 ... R221) to 33 Ohm. 

    6. Added resistor (R134, R191, R234, R237 ... R239, R280 ... R283, R286) [REV03].

  10. Changed RF (J1, J3, J5, J7, J9, J11)[REV02] connector from SMA (5-1814400-1) to SMP (734060241).

  11. Changed RF connector (J2, J4, J6, J8, J10, J12 ... J16)[REV02] from U.FL (U.FL-R-SMT-1) to SMP (734060241).

  12. Changed balun from TCM2-33WX+ to TCM2-43X+ and changed designators from "T" (T2 ... T17) [REV02] to "TR" (TR1 ... TR16) [REV03] with number decreased by one e.g. T2 → TR1.

  13. Changed RF designators from "J" (J1 ... J16) [REV02] to "XS" (XS1 ... XS16) [REV03] e.g. J1 → XS1.

  14. Changed ADC input filter.

    Resistor Designator

    Old resistor value (TEB0835-02-A)

    New resistor value (TEB0835-03-A)

    R7, R8, R35, R36, R21, R22, R49, R50, R14, R15, R42, R43, R28, R29, R56, R57

    590 Ω

    1 MΩ (DNP)

    R6, R9, R34, R37, R20, R23, R48, R51, R13, R16, R41, R44, R27, R30, R55, R58

    17.4 Ω

    0 Ω

  15. Changed DAC output filter.

    Resistor Designator

    Old Value

    New Value

    R63, R64, R70, R71, R77, R78, R84, R85, R91, R92, R98, R99, R105, R106, R112, R113

    590 Ω

    1 MΩ

    R62, R65, R69, R72, R76, R79, R83, R86, R90, R93, R97, R100, R104, R107, R111, R114

    17.4 Ω

    0 Ω

  16. Changed ADC (ADCx_IN to ADC_INx for x = 0 ... 7) and DAC (DACx_OUT to DAC_OUTx for x = 0 ... 7) net names.

  17. Added shield 3670412 (Shield1, Shield2).

  18. Set ADC and DAC clock alternative input circuit to not assembled (J20, J27, J32 ... J35, J38, T26 ... T32, R160, R162, R163, R167, R168, R176, R177, R227, R228, R230, R231, R233, R236)[REV03].

  19. Changed connector (J36) from U.FL (U.FL-R-SMT-1) to SMA (R125426000).

  20. Added RFSoC multi-tile clock via signals "B65_L11_(P/N)" from PLL (U5) signals "CLKOUT8_(P/N)" or via optional external source with not assembled circuit components (J42, T34, R241, R158, R159, C124, C126).

  21. Added RFSoC multi-tile clock via signals "B65_L12_(P/N)" from PLL (U5) signals "CLKOUT7_(P/N)" or via optional external source with not assembled circuit components (J43, T35, R242, R243, R244, C129, C131).

  22. Added syncronisation option for PLL on RFSoC module (TE0835) via signals "EXT_CLK_IN1_P/N". Default single ended clock supply supported via SMA R125426000 (J46), resistor (R224, R287) and signal "EXT_CLK_IN1_P". GND is connected to signal "EXT_CLK_IN1_N" via resistor (R290) in default connection. Optional circuit modification via components (T36, R266, R267) possible.

  23. Changed FireFly connector (J22, J24) from UEC5-019-2-H-D-RA-1 to UEC5-019-1-H-D-RA-1-A and changed pinout (name and order) for high- speed lanes.

  24. Changed FireFly connector (J23, J25) from ECUO to PCUO version.

  25. Added slide switch (S7, R192, R387, R390, R409, R410, R415)[REV03] for FireFly configuration.

  26. Added load switch (Q2, C175 ... C178, C198 ... C201, C212 ... C216, R276, L34, L35) to supply VCC_1.8 FireFly connector (J23 - Pin 9, J25 - Pin 9) power rail.

  27. Added FireFly termination resistor (R246 ... R261, R284, R285, R305, R311, R314, R315, R318, R325, R326, R330 ... R336). Resistor (R246, R248, R250, R252, R254, R256, R258, R260, R285, R305, R315, R318, R330, R331, R334, R335) are not assembled.

  28. Added FireFly resistor (R337 ... R384) detect network.

  29. Added termination resistor (R296 ... R299, R302, R303, R307 ... R310, R312, R313, R317, R320, R403 ... R405, R408) for FireFly connector (J22, J24).

  30. Changed signal names, added pull-up resistor and changed pull-up resistor designator for FireFly signals.

    Old net name (TEB0835-02-A)

    New net name (TEB0835-03-A)

    Old pull-up resistor designator (TEB0835-02-A)

    New pull-up resistor designator (TEB0835-03-A)

    FFA_MPRS

    FF0_PRESENT#

    R191

    R289

    FFA_MSEL

    FF0_SELECT#

    -

    -

    FFA_INTL

    FF0_CPERST#

    -

    R409

    FFA_RSTL

    FF0_CPRSNT#

    -

    R410

    FFB_MPRS

    FF1_PRESENT#

    R194

    R288

    FFB_MSEL

    FF1_SELECT#

    -

    -

    FFB_INTL

    FF1_CPERST#

    -

    R390

    FFB_RSTL

    FF1_CPRSNT#

    -

    R387

  31. Changed capacitor designators for FireFly connectors (J23, J25) and changed 100 nF capacitors from 6.3 V, 0201 to 25 V, 0402.

  32. Changed clock source for signal "SYSREFCLK_P/N" from "CLKOUT7_P/N" [REV02] to "CLKOUT9_P/N" [REV03].

  33.  Connect clock signal "CLKOUT9A_P/N" to B2B connector signal "B65_L13_P/N" and removed it from PLL (U5) feedback clock input. Connected capacitor (C47, C170) at PLL (U5) feedback clock input.

  34. Changed termination for clock signal "CLKIN0_P/N" via capacitor C47 [REV02] PLL (U5) and resistor (R119 [REV02], R120 [REV02]).

  35. Connected PLL (U5) VDD via inductor (L17 [REV03]) to 1.8V instead of using multiple inductors (L17 [REV02], L19 [REV02], L22 [REV02]).

  36. Added pull-up resistor (R294) for signal "DSPLL0_LOL_N".

  37. Changed B2B connector designators:

    Old designator (TEB0835-02-A)

    New designator (TEB0835-03-A)

    J17

    JB1

    J18

    JB2

  38. Changed B2B connector J17 [REV02] / JB1 [REV03] pinout:

    Pin

    Old net (TEB0835-02-A)

    New net (TEB0835-03-A)

    Connected to connector J44

    17

    Not connected

    MIO17

    B18

    19

    Not connected

    MIO18

    B17

    21

    Not connected

    MIO19

    B16

    23

    Not connected

    MIO20

    B14

    25

    Not connected

    MIO21

    A14

    27

    Not connected

    MIO22

    B13

    29

    Not connected

    MIO23

    A13

    31

    Not connected

    MIO24

    B12

    33

    Not connected

    MIO13/25

    A8

    35

    Not connected

    MIO38

    A12

    37

    Not connected

    MIO39

    A7

    38

    Not connected

    MIO26

    B8

    39

    Not connected

    MIO40

    A9

    40

    Not connected

    MIO27

    B5

    41

    Not connected

    MIO41

    A5

    42

    Not connected

    MIO30

    B7

    44

    Not connected

    MIO31

    B3

    46

    Not connected

    MIO34

    B4

    47

    Not connected

    MIO44

    B9

  39. Changed B2B connector J18 [REV02] / JB2 [REV03] pinout:

    Pin

    Old net (TEB0835-02-A)

    New net (TEB0835-03-A)

    Connected to connector J44

    1

    Not connected

    GND

    GND

    2

    Not connected

    GND

    GND

    36

    Not connected

    CLKA_P

    J45 Pin A2

    38

    Not connected

    CLKA_N

    J45 Pin B1

    15

    Not connected

    B65_L1_P

    J45 Pin B7

    17

    Not connected

    B65_L1_N

    J45 Pin A8

    6

    Not connected

    B65_L2_P

    J45 Pin B13

    4

    Not connected

    B65_L2_N

    J45 Pin A14

    3

    Not connected

    B65_L3_P

    J45 Pin B12

    5

    Not connected

    B65_L3_N

    J45 Pin A12

    14

    Not connected

    B65_L4_P

    J45 Pin B16

    12

    Not connected

    B65_L4_N

    J45 Pin A17

    10

    Not connected

    B65_L5_P

    J45 Pin B15

    8

    Not connected

    B65_L5_N

    J45 Pin A15

    11

    Not connected

    B65_L6_P

    J45 Pin B9

    13

    Not connected

    B65_L6_N

    J45 Pin A9

    19

    Not connected

    B65_L8_P

    J45 Pin B6

    21

    Not connected

    B65_L8_N

    J45 Pin A6

    7

    Not connected

    B65_L9_P

    J45 Pin B10

    9

    Not connected

    B65_L9_N

    J45 Pin A11

    22

    Not connected

    B65_L11_P

    CLKOUT8_N via C118

    20

    Not connected

    B65_L11_N

    CLKOUT8_P via C127

    18

    Not connected

    B65_L12_P

    CLKOUT7_N via C128

    16

    Not connected

    B65_L12_N

    CLKOUT7_P via C137

    25

    Not connected

    B65_L13_P

    CLKOUT9A_P via C132

    23

    Not connected

    B65_L13_N

    CLKOUT9A_N via C133

    24

    Not connected

    B65_L16_P

    B18

    26

    Not connected

    B65_L16_N

    A18

    156

    Not connected

    EXT_CLK_IN1_P

    J46 via R224 and R287 (default) or J46 via R224 and T36 Pin 1 (optional)

    158

    Not connected

    EXT_CLK_IN1_N

    GND via R290 (default) or GND via T36 Pin 3

  40. Added 100 Ohm clock termination resistor for signals "CLKD_P/N" (R120 [REV03]), "CLKE_P/N" (R291) and "CLKF_P/N" (R193 [REV03]).

  41. Changed power supply structure for FTDI (U12) interface.

    1. Changed USB net name "USB_VBUS" to "5V_VBUS".

    2. Added power supply circuit (U19, D6, D7, C220, C217, L19 [REV03], C171, R273 (optional), R274 (optional)) to provide power rail "3.3V_FTDI" to FTDI chip (U12).

    3. Possible power supply for LDO (U19) via power rail "5V_VBUS" (D6) or/and "V_5V0" (D7).

    4. Supply EEPROM (U15), oscillator (U16) and FTDI chip (U12) from power net "3.3V_FTDI".

  42. Changed buffer (U13, U14) from SN74LVC1G07DRL to SN74AVC4T774RSVR and adapted according circuits. Used buffer (U13) for tri-stating JTAG signals and buffer (U14) for UART signal voltage translation. Removed series resistor (R237 ... R240) for JTAG signals.

  43.  Added optional connection between FTDI chip (U12) signal ADBUS4 and power net 3.3V_FTDI via pull-up resistor (R124).

  44. Added USB filter (L25) for FTDI USB signals.

  45. Removed FTDI EEPROM AMD-Licence key (MISC1).

  46. Set resistor (R223) as not assembled to set USB mode.

  47. Added connector (J44, J45, L26 (default: not assembled), L27, L40, L41, C183 ... C185, C208 ... C211).

  48. Added TE0835 front panel (MECH1), screws (MECH3, MECH4) and PCB Spacer (MP1 ... MP4).

  49. Added light pipe (LP1).

  50. Changed MEMS oscillator (U16) from SiT8008AI-73-XXS-12.000000E to SiT8008BI-73-XXS-12.000000E.

  51. Changed LED (D1 ... D3) from SML-P11MTT86R to LG R971-KN-1-0-20-R18.

  52. Changed MOSFET (T18 ... T21) from SIS444DN-T1-GE3 to SIS4604LDN-T1-GE3.

  53. Changed following resistors:

    1. 4.7 kOhm resistor (R157, R202) from 0.05 W, 0201 to 0.063 W, 0402.

    2. 33 Ohm resistor (R208) from 0.05 W, 0201 to 0.063 W, 0402.

  54. Changed ferrite bead (L12) from BKP0603HS121-T to BLM15PX121SN1D.

  55. Changed ferrite bead (L10, L11) from LI0402E300R-10 to BLM15PX121SN1D.

  56. Changed inductor (L4, L5, L7, L8) from VLS3012HBX-1R0M to LPWI252010S1R0T.

  57. Changed following capacitors:

    1. 100 nF capacitor (C4 ... C35, C47, C50, C52 ... C54, C56, C57, C68, C77, C104, C106 ... C112, C115 ... C118, C143, C144, C146, C149, C150, C153, C154, C157, C158, C161, C162, C165, C166, C169) from 6.3 V, X5R, 0201 to 50 V, X7R, 0402.

    2. 100 nF capacitor (C88 ... C97) from X5R to X7R. 

    3. Capacitor (C123) from 100 nF, 6.3 V, X5R, 0201 to 220 nF, 50 V, X7R, 0603.

    4. 470 nF capacitor (C145) from 0201 to 0402.

    5. Capacitor (C135) from 100 nF, 0201 to 1 µF, 0402.

    6. Capacitor (C44, C46, C48, C49, C132, C133) from 10 V, 0201 to 50 V, 0402.

  58. Changed unused MOSFET (T33B) inputs from short to GND to floating pins.

  59. Changed I2C signal names and designators for I2C pull-up resistors.

    Old net (TEB0835-02-A)

    New net (TEB0835-03-A)

    Old pull-up resistor designator (TEB0835-02-A)

    New pull-up resistor designator (TEB0835-03-A)

    FFB_SCL

    FF0_SCL

    R196

    R262

    FFB_SDA

    FF0_SDA

    R195

    R263

    FFA_SCL

    FF1_SCL

    R193

    R264

    FFA_SDA

    FF1_SDA

    R192

    R265

  60. Added test point (TP22 ... TP34, TP45).

  61. Changed fiducials to standard fiducial type.

  62. Added UKCA-logo.

  63. Added I2C address table, power overview and clock overview. Updated legal notices, system overview and revision history. Updated page count and order.

REV03

PCN

2020-08REV02
  1. All module's mount holes are connected to GND.
  2. CLK_Connectors. Added baluns for each clock inputs.
  3. Internal DSPLL is changed on SI5395A-A-GM.
  4. Added ability to use internal DSPLL as a source for each clock.
  5. Added clock inputs CLKIN1, CLKIN2 and clock outputs OUT1 , OUT2 connected to DSPLL.
  6. All clock traces are matched with tolerance 0.2 mm.
  7. Lengths of inputs ADC0, ADC2, ADC4, ADC6 are matched with tolerance 0.2 mm.
  8. Lengths of outputs DAC0 and DAC2 are matched with tolerance 0.2 mm.
  9. Lengths of outputs DAC4, DAC5, DAC6, DAC7 are matched with tolerance 0.2 mm.
  10. In REV02: FTDI is powered from 3.3V_Module.
  11. Signal PLL_INTR_N is removed.
  12. Signal BOARD_PG is renamed in MODULE_PG.
  13. Added ability to select enable signal for internal DC-DCs 3.3V and 1.8V.
  14. Added JTAG connector J40.
  15. Added VBAT schematic. Added a holder for CR1220 3V battery.
  16. Resistor R4 changed to 10K (was 1K)

REV02

PCN

2019-12REV01Initial ReleaseREV01
Hardware Revision History

Document Change History

DateRevisionContributorDescription

v.59

Kilian Jahn

  • Modified DrawIO settings to standard

  • Added warning for U15 into On-board Peripherals

2025-10-09

V.57

Kilian Jahn

  • Updated to new TRM template revision 4.3

  • Updated to hardware revision 3

2024-08-27

v.56

John Hartfiel

  • Board to Board Connector section: Bugfix for Include Macro

2023-08-04

v.55

Manuela Strücker 

  • Update download link
2023-01-17v.54Kerstin Möller
  • Style update
2020-12-21v.51Pedram Babakhani
  • Update to 
    revision 02

--

all

Pedram Babakhani , John Hartfiel , Kilian Jahn , Kerstin Möller , Manuela Strücker

  • --
Document change history.

Disclaimer

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Technology Licenses

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REACH

Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).

RoHS

Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.

WEEE

Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).

Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.



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