• Last modified: May 13, 2025
 

Overview

CPLD Device with designator U21: LCMX02-256HC

Feature Summary

  • JTAG routing
  • Boot Mode (SD, QSPI, JTAG or eMMC)
  • PUDC
  • CPLD Register Info via I²C
  • GPIO expansion via I²C (PCA9538 Emulator)
  • (User) LED

Firmware Revision and supported PCB Revision

See Document Change History

Product Specification

Port Description

NameDirectionPinI/O BankPullmodeIO_TypeDescription
C_TCKin300NONELVCMOS33

JTAG B2B

  • maxdelay from port "TCK" to port "C_TCK" is 10ns
C_TDIin320UPLVCMOS33

JTAG B2B

  • maxdelay from port "TDI" to port "C_TDI" is 10ns
C_TDO out10NONELVCMOS33

JTAG B2B

  • maxdelay from port "C_TDO" to port "TDO" is 10ns
  • slewrate=fast
C_TMSin290UPLVCMOS33

JTAG B2B

  • maxdelay from port "TMS" to port "C_TMS" is 10ns
RST_ENinout270UPLVCMOS33

Reset input signal

  • by default R113 is not populated so default is RST
USR_LEDout43NONELVCMOS33

Priority dependend User LED - Blink Code, see chapter User LED 

PG_ALLin53NONE

LVCMOS33

Power good input signal

JTAGENin260---LVCMOS33

Enable JTAG access to CPLD for Firmware update

  • 0: JTAG routed to module
  • 1: CPLD access
MODEin250UPLVCMOS33

Boot Mode for ZynqMP Devices

  • used in combination with PGOOD pin for Boot mode selection, see chapter Boot Mode
MODE0out122NONELVCMOS18

ZynqMP Boot Mode Pin 0

  • slewrate=slow
  • drive strength=4
MODE1out132NONELVCMOS18

ZynqMP Boot Mode Pin 1

  • slewrate=slow
  • drive strength=4
MODE2out142NONELVCMOS18

ZynqMP Boot Mode Pin 2

  • slewrate=slow
  • drive strength=4
MODE3out162NONELVCMOS18

ZynqMP Boot Mode Pin 3

  • slewrate=slow
  • drive strength=4
NOSEQinout230UPLVCMOS33

No Sequencing

  • Used as GPIO pin by user. Mapped to gpio expander (PCA Emulator)
PGOODinout280UPLVCMOS33

Dual use of PGOOD

  • used in combination with MODE pin for Boot mode selection, see chapter Boot Mode
  • used as Power Good output signal, see chapter Power
PUDC_Bout172NONELVCMOS18

Pull up during configuration

  • SoC disabled IOs will be 3-stated after power-on
TCKout92NONELVCMOS18

JTAG ZynqMP

  • maxdelay from port "TCK" to port "C_TCK" is 10ns
  • slewrate=fast
TDIout82NONELVCMOS18

JTAG ZynqMP

  • maxdelay from port "TDI" to port "C_TDI" is 10ns
  • slewrate=fast
TDOin102NONELVCMOS18

JTAG ZynqMP

  • maxdelay from port "C_TDO" to port "TDO" is 10ns
TMSout112NONELVCMOS18

JTAG ZynqMP

  • maxdelay from port "TMS" to port "C_TMS" is 10ns
  • slewrate=fast
X0in201UPLVCMOS18Used as SCL I²C clock pin
X1inout211UPLVCMOS18Used as SDA I²C data pin

Functional Description

JTAG

JTAG signals routed directly through the CPLD to FPGA. Access between CPLD and FPGA can be multiplexed via JTAGEN (logical one for CPLD, logical zero for FPGA) on JM1-89.

Power

There is no additional power management controlled by CPLD. PGOOD output signal is feedback from PG_ALL input signal.

Reset

RST_EN is used as reset input signal.

PUDC_B

Constant 1 →  The I/Os will be 3-stated after power-on when PUDC_B is High.

Boot Mode (SD, QSPI, JTAG or eMMC)

Boot mode adjustment via Software is removed as it is adjustable via XSCT console and to keep the code as simple as necessary. → BootMode via XSCT

Boot mode can be changed between SD, QSPI, JTAG or eMMC. Due to too few input pins, the PGOOD pin is used as an additional input pin. If necessary, variants without additional PGOOD pin can be provided on request (SD/QSPI, JTAG/QSPI, SD/JTAG). For other UltraScale+ Boot Modes options custom firmware is needed, see also Table 11.1 Boot Modes from Xilinx UG1085.

Boot mode

PGOOD

(B2B JM1-30)

Mode

(B2B JM1-32)

comments
SD1 (SD card)10

with carrier TE0703 Dip Switch

  • S2-1: OFF
  • S2-4: ON
QSPI11

with carrier TE0703 Dip Switch

  • S2-1: OFF
  • S2-4: OFF
JTAG00

with carrier TE0703 Dip Switch

  • S2-1: ON
  • S2-4: ON
SD0 (eMMC)01

with carrier TE0703 Dip Switch

  • S2-1: ON
  • S2-4: OFF

I2C info core

The I2C_info_core module provides read-only access to configuration and status registers (8-bit) implemented inside the CPLD. These registers are exposed via an I²C interface and follow a simple address-based protocol. The block uses I²C chip address 0x20 on I²C bus 1.

Access Registers from Linux

To read register from Linux

root# i2cget -y 1 0x20 <Index>

Where <index> is the register address described below

CPLD Register Map
IndexBitsNameDescriptionDefault
0x00

[7:0]

CPLD_REVISION_MAJORMajor CPLD firmware revision0x02
0x01

[7:0]

CPLD_REVISION_MINORMinor CPLD firmware revision0x00
0x02

[3:0]

boot_mode_i

Boot mode indicator: 

  • 0x0 : JTAG
  • 0x2 : QSPI
  • 0x3 : SD0 (eMMC)
  • 0x5 : SD1 (SD card)

—

0x3

[7:0]

GIT_HASH[7:0]

32-bit GIT commit hash of CPLD Firmware




0x9E0B18EC
0x4

[7:0]

GIT_HASH[15:8]
0x5

[7:0]

GIT_HASH[23:16]
0x6

[7:0]

GIT_HASH[31:24]
0x7

[3:0]

BOOTMODE_VARIANT


Bootmode variant (depending on firmware):

  • 0x0 : QSPI/SD
  • 0x1 : QSPI/JTAG
  • 0x2 : JTAG/SD
  • 0x3 : QSPI/JTAG/SD/eMMC (default)

0x3

0x8

[7:0]

PUDC

Read generic PUDC (depending on firmware):

  • 0 --> PULLUP enabled
  • 1 --> PULLUP disabled IOs will be 3-stated after power-on

0x1


PCA9538 Emulator (GPIO expansion)

The gpio_expander module implements a VHDL-based PCA9538-compatible I²C GPIO expander core. It is accessible via I²C chip address 0x42 on I²C bus 1. Since the PCA9538 has robust driver support in both Linux and U-Boot, this module can be seamlessly integrated using the Device Tree. It works with common tools such as:

  • libgpiod (Linux user-space GPIO access)

  • gpioset, gpioget (Linux CLI)

  • gpio (U-Boot command)

Accessing GPIOs from U-Boot
Show GPIO status
ZynqMP> gpio status -a
Example output:
....
Bank gpio@42:
gpio@42_0: input: 0 [ ]
gpio@42_1: input: 0 [ ]
....
Set GPIO value
ZynqMP> gpio set gpio@42_0
gpio: pin gpio@42_1 is one

This sets GPIO 0 of I²C chip address 0x42 to high.

Accessing GPIOs from Linux
Detect GPIOs
root# gpiodetect
Example output:
gpiochip0 [a40a0000.gpio] (2 lines)
gpiochip1 [a40b0000.gpio] (8 lines)
gpiochip2 [a40c0000.gpio] (12 lines)
Set GPIO value
gpioset 2 0=1

This sets line 0 of gpiochip2 (i.e., GPIO index 0) to high.

CPLD GPIO Register Mapping
gpiochipLineGPIO PinDescriptionDefault
2

0

NOSEQ

Output control:

  • 0 : Signal low
  • 1 : Signal high
1
2

1

USR_LED

Output control:

  • 0 : Signal low
  • 1 : Signal high
0

User LED - Priority-Based Blink Code

The User LED D2 indicates various system states using an 8-bit blink pattern. The pattern plays in a loop and reflects system status based on priority — higher-priority conditions override lower-priority ones.

PriorityPatternDescription

0

*0000000

Power good failed

1

******00

Reset enabled

2

********

PGOOD = '0' - JTAG or eMMC Boot mode

3

(custom)User-defined via I²C register

4

'0'Default/inactive state

Each asterisk (*) represents a short flash; each o represents an off-state of the same duration. For example, a pattern of **oooooo means 2 short flashes followed by a pause equal to six flash durations.

NOSEQ pin

As module power management is not supported for this series, NOSEQ is used as GPIO pin. It can be accessed via I²C interface.

PGOOD pin

Dual use pin.

  • PGOOD output signal
  • During reset PGOOD pin is used as boot mode pin

Appx. A: Change History

Revision Changes

  • REV01 to REV02.00
    • PCB REV02 support only
    • changed name of generic parameter from VARIANT to BOOTMODE_VARIANT
    • added generic parameter CPLD_REVISION_MAJOR/MINOR, GIT_HASH & PUDC
    • added port signal 'PG_ALL'
    • renamed port signal 'User_LED' to 'USR_LED'
    • PGOOD
      • changed PULLMODE of port signal 'PGOOD' from DOWN to UP
      • PGOOD pin used as boot mode selector pin
    • EN1/RST_EN
      • renamed port signal 'EN1' to 'RST_EN'
      • by default R113 is not populated so default is RST
    • changed PULLMODE of port signal 'NOSEQ' from NONE to UP
    • added library work.types_pkg.all
    • adapted libraries
    • Removed component ROM128X1A
    • added JTAG time constraint
    • Changed functionality of FPGA IOs X0/X1
      • added component I2C_info_core for CPLD information
      • added component gpio_expander.vhd (PCA9535_Emulator)
    • LED function changes
      • added component led_blink_codes.vhd
      • *ooooooo  -- PG_ALL failed
      • ******oo  -- Reset enabled
      • ********  -- PGOOD = 0
      • USER dependent
      • else '0'
    • renamed signal bood_mode_i to boot_mode_i
  • REV00 to REV01
    • copy of TE0820 CPLD Firmware
    • changed PHY_LED1 in to PUDC_B out
    • X0/X1 connected to other FPGA IOs

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

DateDocument RevisionCPLD Firmware RevisionSupported PCB RevisionAuthorsDescription

v.18

REV02.00REV02 Manuela Strücker


  • release PCB Rev02
2019-10-30v.4REV01REV01

John Hartfiel

  • first release

All

Manuela Strücker


Appx. B: Legal Notices

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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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