- Created by Mohsen Chamanbaz, last modified on 16 08, 2023
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Overview
Refer to http://trenz.org/tem0007-info for the current online version of this manual and other available documentation.
Key Features
- Libero SoC v2023.1
- SoftConsole v2022.2-RISC-V-747
- PolarfireSoC MSS Configurator v2023.1
- HSS (Hardware System Service)
- Yocto
- UART
- ETH
- USB
- I2C
- QSPI flash
- DDR3 memory
- User LED
Revision History
Date | Libero SoC | Project Built | Authors | Description |
---|---|---|---|---|
2023-08-16 | v2023.1 | Mohsen Chamanbaz |
|
Release Notes and Know Issues
Issues | Description | Workaround | To be fixed version |
---|---|---|---|
No known issues | --- | --- | --- |
Requirements
Software
Software | Version | Note |
---|---|---|
Libero SoC | v20223.1 | needed |
SoftConsole | v2022.2 | needed |
PolarfireSoC MSS Configurator | v2023.1 | needed |
Yocto | Kirkstone | needed (more information: |
Hardware
Complete List is available on <project folder>/board_files/*_board_files.csv
Design supports following modules:
Module Model | Board Part Short Name | Yocto Machine Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
---|---|---|---|---|---|---|---|---|
TEM0007-01-S002* | 25_1E0_ES_1GB | tem0007 | REV01 | 1GB | 64MB | ---- | ---- | ---- |
TEM0007-01-CHE11-A | 250_1E_1GB | tem0007 | REV01 | 1GB | 64MB | ---- | ---- | ---- |
*used as reference
Design supports following carriers:
Carrier Model | Notes |
---|---|
Modified TE0703* | As carrier board. This board must be modified. For more information see Modified TE0703 for Microchip Getting Started |
*used as reference
Additional HW Requirements:
Additional Hardware | Quantity | Notes |
---|---|---|
TE0790 XMOD | 1 | For HSS console |
Mini USB cable for JTAG/UART | 2 | Check Carrier Board and Programmer for correct type |
RJ45 Ethernet cable | 1 |
*used as reference
Content
For general structure and usage of the reference design, see Project Delivery - Microchip devices
Design Sources
Type | Location | Notes |
---|---|---|
Libero | <project folder>/source_files/Libero <project folder>/source_files/<Board Part Short Name>/Libero | Libero project will be generated by TE Scripts (Optional) Source files for specific assembly variants |
SoftConsole | <project folder>/source_files/SoftConsole <project folder>/source_files/<Board Part Short Name>/SoftConsole | Additional software will be generated by TE Scripts (Optional) Source files for specific assembly variants |
Yocto | <project folder>/source_files/os/yocto | Yocto BSP layer template for linux |
Prebuilt
File | File-Extension | Description |
---|---|---|
Libero Project File | *.prjx | |
FlashPro Express Job | *.job | |
Constraint File | *.pdc | |
Timing Constraint File | *.sdc | |
Components in Block Design | *.cxf | |
Configuration File | *.cfg | |
Software-Application-File | *.elf | Software application for SoftConsole |
Device Tree | *.dtb | Device tree blob |
CONF-File | *.conf | Boot configuration file (extlinux.conf) |
Yocto linux image | *.wic | This File can be flashed via bmaptool on the SD card. |
Yocto linux image | *.img | Linux image for SD card |
Download
Reference Design is only usable with the specified Libero version. Do never use different versions of Libero software for the same project.
Reference Design is available on:
Design Flow
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.
Trenz Electronic provides a tcl based built environment based on Libero Design Flow.
See also:
The most Trenz Electronic FPGA Reference Designs are TCL-script based projects.
The "normal" Libero project will be generated in the subfolder "/Libero/" and the additional software part will be generated in the subfolder "/software/" after executing scripts.
To create project do the following steps:
- Execute "create_project_win.cmd" or "create_project_linux.sh"
- Select your board in "Board selection" , if there is more than one variant.
- Choose one of the following options::
- Press 0 , if it will enter the full path of Libero SoC TCL shell.
- Press 1, if it will enter the full path of Microchip installation folder. For example "c:\Microchip\"
- Press 2, if it will enter folder path or drive to search for variable TCL shell and select from generated list elements.
- Press x to exit script.
- Choose one of the following options:
- Press 0 to use Libero SoC at its path. For example Libero_SoC_v2022.2 at C:/Microchip/Libero_SoC_v2022.2
- Press 1 to enter path of installation folder of Microchip or Libero SoC
- Press 2 to enter full path of Libero SoC exe file
- Press 3 to exit th script
- Choose one of the following options:
- Press 0 to overwrite old Libero project folder , if it exists.
- Press 1 to to generate another project folder
- Press 2 to to enter own Libero project folder name
- Press 3 to exist script and do not generate the hardware design
- Waiting to be completed the generation of new project , if a new project is desired.
- Press y to open the generated Libero SoC project.
Launch
Programming
Check Module and Carrier TRMs for proper HW configuration before you try any design.
Programming eNVM in SoftConsole
To program HSS *.elf file on FPGA:
- Connect the TEM0703 board via its Mini-USB connector. (J4)
- Open SoftConsole software as administrator, if it is not done yet.
- Select correct directory as workspace directory.
- Build the hart-software-services-master , if it is not done yet.
- Click on Run > External Tools > Polarfire SoC program non-secure boot-mode 1
Programming Bitstream
There is two ways to program bitstream file on FPGA:
Using Libero SoC
- Connect the TEM0703 board via its Mini-USB connector. (J4)
- After generating bitstream in Libero click on Run PROGRAM Action to program bitstream file on FPGA.
Using FPExpress software
- Connect the board via USB connector
- Export *.job file , if does not exist yet.
- Click on new
- Give path of job file by clicking on Browse
- Click on OK
- Click on RUN
Get prebuilt boot binaries
Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.
Run create_project_win.cmd/create_project_linux.shSelect Module in 'Board selection'Click on 'Export prebuilt files' buttonFolder <project folder>/_binaries_<Article Name> with subfolder boot_linux will be generated and opened
SD-Boot mode
Prepare SD card as follows for SD-Boot.
There are two commands to write image file on the SD card after mounting SD card in the host linux same as WSL:
- Insert SD card in the SD card reader
bmaptool copy --nobmap <Path of image file *.img> /dev/sdX
- After mounting the SD card in linux the name of SD card recognized via lsblk command. For example SD card name can be sda or sdb.
dd if=<Path of image file *.img> of=/dev/sdX
- After mounting the SD card in linux the name of SD card recognized via lsblk command. For example SD card name can be sda or sdb.
Alternative SD card can be written via Win32DiskImager or balenaEtcher softwares in Windows OS.
JTAG
Not used on this example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Connect your board to the network
- Power on PCB
UART
- Open Serial Console (e.g. PuTTY)
select COM Port
Win OS: see device manager
Linux OS: see dmesg | grep tty (UART is *USB1)
- Speed: 115200
- Press reset button
- Console output depends on used Software project, see Software Design - SDK#Application
- Linux Console:
Login data:
Note: Wait until Linux boot finished
tem0007 login: root
You can use Linux shell now.
i2cdetect -y -r 1 (check I2C 1 Bus) dmesg | grep rtc (RTC check) udhcpc (ETH0 check) lsusb (USB check)
- ...
System Design - Libero
Block Design
The block designs may differ depending on the assembly variant.
HPS Interfaces
Activated interfaces:
Type | Note |
DDR | -- |
EMAC0 | -- |
EMAC1 | -- |
GPIO0 | -- |
GPIO1 | -- |
GPIO2 | -- |
I2C0 | -- |
I2C1 | -- |
QSPI | -- |
SDMMC | -- |
UART0 | -- |
UART1 | -- |
USB0 | -- |
USB1 | -- |
CAN0 | -- |
CAN1 | -- |
Software Design - SoftConsole
Application
Used software project depends on board assembly variant. Template location: <project folder>/source_files/software/
...
HSS (Hart Software Service)
This is Hart Software Services (HSS) code.On PolarFire SoC, this is comprised of two portions:
A superloop monitor running on the E51 minion processor, which receives requests from the individual U54 application processors to perform certain services on their behalf;
A Machine-Mode software interrupt trap handler, which allows the E51 to send messages to the U54s, and request them to perform certain functions for it related to rebooting a U54.
The HSS performs boot and system monitoring functions for PolarFire SoC. The HSS is compressed (DEFLATE) and stored in eNVM. On power-up, a small decompressor wrapper inflates the HSS from eNVM flash to L2-Scratchpad memory and starts the HSS.
Creating HSS workspace in SoftConsole
- Download the HSS folder here: hart-software-services
- Unzip the hart-software-services-master zip file in the SoftConsole workspace
- Open SoftConsole software as administrator
- Select correct directory as workspace directory. The workspace folder must consist of hart-software-services-master folder
- Right click on board folder in the left side and click on new folder
- Rename the folder for desired board. For example for TEM0007 module rename it to TEM0007. If there is TEM0007, this HSS workspace was created already and HSS is ready to be compiled.
- Create other subfolders as shown (For example for TEM0007):
- hart-software-serevices-master
- board
- TEM0007
- drivers_config
- fpga_ip
- miv_ihc
- Copy miv_ihc_add_mapping.h and miv_ihc_config.h files from original folder of icicle kit board ( mpfs-icicle-kit-es ) and paste in this folder.
- miv_ihc
- fpga_ip
- fpga_design_config
- This folder should be left empty. After compiling the neccessary header files for ddr, clock, IOs and other properties of desired module and hardware design will be generated and saved in this folder by mpfs_configuration_generator.py python script. The python script is saved already in the tools/polarfire-soc-configuration-generator folder.
- This folder should be left empty. After compiling the neccessary header files for ddr, clock, IOs and other properties of desired module and hardware design will be generated and saved in this folder by mpfs_configuration_generator.py python script. The python script is saved already in the tools/polarfire-soc-configuration-generator folder.
- mpfs_hal_config
- Copy mss_sw_config.h file from original folder of icicle kit board ( mpfs-icicle-kit-es ) and paste
- Copy mss_sw_config.h file from original folder of icicle kit board ( mpfs-icicle-kit-es ) and paste
- soc_fpga_design
- xml
- Copy the generated xml with PolarFireSoC MSS Configurator software here. For example TEM0007_MSS_mss_cfg.xml
- Copy the generated xml with PolarFireSoC MSS Configurator software here. For example TEM0007_MSS_mss_cfg.xml
- xml
- Copy the following files from original folder of icicle kit board ( mpfs-icicle-kit-es ) and paste in this folder (TEM0007 folder) :
- hss_board_init.c
- hss_usrt_init.c
- usrt_helper.c
- hss_I2Scratch.lds
- Kconfig
- Edit Kconfig for example for TEM0007 module as shown:Kconfig
menu "TEM0007 Design Configuration Options" config SOC_FPGA_DESIGN_XML string "Enter path to Libero XML file" default "boards/$(BOARD)/soc_fpga_design/xml/TEM0007_MSS_mss_cfg.xml" help This option specifies the design XML file to use. endmenu
- Edit Kconfig for example for TEM0007 module as shown:
- drivers_config
- TEM0007
- board
- hart-software-serevices-master
- Makefile
- Edit Makefile for example for TEM0007 module as shown:Makefile of TEM0007 folder
- Edit Makefile for example for TEM0007 module as shown:
- Makefile
- Edit Makefile in hart-software-services-master Folder for example for TEM0007 as shown:Makefile of hart-software-services-master folder
- Copy def_config file from original folder of icicle kit board ( mpfs-icicle-kit-es ) and paste it in hart-software-services-master folder and rename it to .config file.
- Edit .config file according to your module. For example for TEM0007 is edited this file as shown:.config File
- Edit .config file according to your module. For example for TEM0007 is edited this file as shown:
- Now HSS workspace is ready to be compiled. Right click on hart-software-services-master and click on Build Project.
- After compiling a config.h will be generated in the hart-software-services-master folder. By opening this header file it can be seen all configurations of .config file.
Software Design - Yocto
Trenz electronic has developed his own BSP for Microchip devices same as polarfire soc in Yocto. In the following will be explained the folders in detail.
meta-trenz-polarfire-bsp Folder | Description |
---|---|
recipes-apps | Contains of start up application for executing of init.sh by booting. |
recipes-bsp | Contains of uboot necessary files same as *.bbappend files, device tree and etc. |
recipes-core | Contains of *.bb file for Trenz defined image version. In this file are defined necessary packets or files that must be installed in linux. |
recipes-kernel | Contains of kernel necessary files same as *.bbappend files, device tree, config files and etc. |
recipes-tools | Contains of *.bbappend file |
tools | Contains of manifest xml file to define necessary meta data that are required. |
In the following table exists more information about required packets and supported version.
Meta data | Supported Version | Description |
---|---|---|
meta-riscv | Kirkstone | |
openembedded-core | Kirkstone | |
meta-openembedded | Kirkstone | |
meta-polarfire-soc-yocto-bsp | 2022.11 |
Trenz BSP contains of a shell script. If this shell script in be executed , all required processes for making a linux image file will be executed. The user needs only to write the image file on the SD card. To prepare the image file :
- Download and save meta-trenz-polarefile-bsp folder in the host linux
. ./meta-trenz-polarfire-bsp/trenz_polarfire_setup.sh
- After compiling image file *.img and its converted zip file *.zip will be in trenz bsp folder saved :
- <trenz bsp folder>/prebuilt/boot/yocto/SD_Card.img
- <trenz bsp folder>/prebuilt/boot/yocto/SD_Card.zip
For Yocto installation and project creation, follow instructions from:
U-Boot
Start with Create a custom BSP layer for Microchip SoC or FPGA#Configure u-boot
File location: meta-<module>/recipes-bsp/u-boot/
Changes:
- No changes
Device Tree
U-boot Device Tree
// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* * Copyright (C) 2021 Microchip Technology Inc. * Padmarao Begari <padmarao.begari@microchip.com> */ /dts-v1/; #include "microchip-mpfs.dtsi" #include "dt-bindings/gpio/gpio.h" /* Clock frequency (in Hz) of the rtcclk */ #define RTCCLK_FREQ 1000000 / { model = "Microchip PolarFire-SoC Icicle Kit"; compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; aliases { serial1 = &uart1; ethernet0 = &mac0; spi0 = &qspi; }; chosen { stdout-path = "serial1"; }; cpus { timebase-frequency = <RTCCLK_FREQ>; }; ddrc_cache: memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; clocks = <&clkcfg CLK_DDRC>; status = "okay"; }; }; &uart1 { status = "okay"; }; &mmc { status = "okay"; bus-width = <4>; disable-wp; cap-mmc-highspeed; cap-sd-highspeed; cd-debounce-delay-ms; card-detect-delay = <200>; mmc-ddr-1_8v; mmc-hs200-1_8v; sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; sd-uhs-sdr104; }; &i2c1 { status = "okay"; clock-frequency = <100000>; }; &mac1 { status = "disabled"; }; &mac0 { status = "okay"; phy-mode = "sgmii"; phy-handle = <&phy0>; phy0: ethernet-phy@1 { device-type = "ethernet-phy"; reg = <1>; reset-names = "ETH_RST"; reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; }; &qspi { status = "okay"; num-cs = <1>; flash0: spi-nor@0 { compatible = "spi-nor"; reg = <0x0>; spi-tx-bus-width = <4>; spi-rx-bus-width = <4>; spi-max-frequency = <20000000>; spi-cpol; spi-cpha; }; };
Kernel Device Tree
// SPDX-License-Identifier: (GPL-2.0 OR MIT) /* Copyright (c) 2020-2021 Microchip Technology Inc */ /dts-v1/; #include "mpfs.dtsi" #include "mpfs-icicle-kit-fabric.dtsi" #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/phy/phy.h> /* Clock frequency (in Hz) of the rtcclk */ #define MTIMER_FREQ 1000000 / { #address-cells = <2>; #size-cells = <2>; model = "Microchip PolarFire-SoC Icicle Kit"; compatible = "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpfs-icicle-kit", "microchip,mpfs"; aliases { ethernet0 = &mac0; serial0 = &mmuart0; serial1 = &mmuart1; serial2 = &mmuart2; serial3 = &mmuart3; serial4 = &mmuart4; }; chosen { stdout-path = "serial1:115200n8"; }; cpus { timebase-frequency = <MTIMER_FREQ>; }; //******************************************************// ddrc_cache: memory@80000000 { device_type = "memory"; reg = <0x0 0x80000000 0x0 0x40000000>; status = "okay"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; fabricbuf0ddrc: buffer@A0000000 { compatible = "shared-dma-pool"; reg = <0x0 0xA0000000 0x0 0x2000000>; no-map; }; }; udmabuf0 { compatible = "ikwzm,u-dma-buf"; device-name = "udmabuf-ddr-c0"; minor-number = <0>; size = <0x0 0x2000000>; memory-region = <&fabricbuf0ddrc>; sync-mode = <3>; }; //******************************************************// usb_phy: usb_phy { #phy-cells = <0>; //compatible = "ulpi-phy"; compatible = "usb-nop-xceiv"; reset-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>; reset-names = "OTG_RST"; }; soc { }; }; &can0 { status = "disabled"; }; &core_pwm0 { status = "okay"; }; &fpgadma { status = "okay"; }; &fpgalsram { status = "okay"; }; &gpio1 { status = "okay"; }; &gpio2 { interrupts = <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>, <53>; status = "okay"; }; &i2c0 { status = "okay"; }; &i2c1 { status = "okay"; #address-cells = <1>; #size-cells = <0>; eeprom: eeprom@50 { compatible = "atmel,24c02"; reg = <0x50>; #address-cells = <1>; #size-cells = <1>; eth0_addr: eth-mac-addr@FA { reg = <0xFA 0x06>; }; }; }; &i2c2 { status = "okay"; }; &mac0 { status = "okay"; phy-mode = "sgmii"; nvmem-cells = <ð0_addr>; nvmem-cell-names = "mac-address"; /delete-property/ local-mac-address; phy-handle = <&phy0>; phy0: ethernet-phy@1 { device-type = "ethernet-phy"; reg = <1>; reset-names = "ETH_RST"; reset-gpios = <&gpio1 16 GPIO_ACTIVE_LOW>; }; }; &mac1 { status = "disabled"; }; &mbox { status = "okay"; }; &mmc { status = "okay"; bus-width = <4>; disable-wp; cap-sd-highspeed; cap-mmc-highspeed; mmc-ddr-1_8v; mmc-hs200-1_8v; sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; sd-uhs-sdr104; }; &mmuart1 { status = "okay"; }; &mmuart2 { status = "okay"; }; &mmuart3 { status = "okay"; }; &mmuart4 { status = "okay"; }; &qspi { status = "okay"; num-cs = <1>; }; &refclk { clock-frequency = <125000000>; }; &spi0 { status = "okay"; }; &spi1 { status = "disabled"; }; &usb { status = "okay"; dr_mode = "otg"; phys = <&usb_phy PHY_TYPE_USB2>; };
Kernel
Start with Create a custom BSP layer for Intel SoC or FPGA#Configure linux kernel
File location: meta-<module>/recipes-kernel/linux/
Changes:
- No changes.
Images
Image recipe for minimal console image
File location: meta-<module>/recipes-images/yocto/
Image recipes:
- te-image-minimal.bb: create minimal linux image
- te-initramfs.bb: required for building an image with initial RAM Filesystem
Added packages/recipes:
- No packages/recipes
Rootfs
Used filesystem: Initial RAM Filesystem (initramfs)
Appx. A: Change History and Legal Notices
Document Change History
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Legal Notices
Data Privacy
Please also note our data protection declaration at https://www.trenz-electronic.de/en/Data-protection-Privacy
Document Warranty
The material contained in this document is provided “as is” and is subject to being changed at any time without notice. Trenz Electronic does not warrant the accuracy and completeness of the materials in this document. Further, to the maximum extent permitted by applicable law, Trenz Electronic disclaims all warranties, either express or implied, with regard to this document and any information contained herein, including but not limited to the implied warranties of merchantability, fitness for a particular purpose or non infringement of intellectual property. Trenz Electronic shall not be liable for errors or for incidental or consequential damages in connection with the furnishing, use, or performance of this document or of any information contained herein.
Limitation of Liability
In no event will Trenz Electronic, its suppliers, or other third parties mentioned in this document be liable for any damages whatsoever (including, without limitation, those resulting from lost profits, lost data or business interruption) arising out of the use, inability to use, or the results of use of this document, any documents linked to this document, or the materials or information contained at any or all such documents. If your use of the materials or information from this document results in the need for servicing, repair or correction of equipment or data, you assume all costs thereof.
Copyright Notice
No part of this manual may be reproduced in any form or by any means (including electronic storage and retrieval or translation into a foreign language) without prior agreement and written consent from Trenz Electronic.
Technology Licenses
The hardware / firmware / software described in this document are furnished under a license and may be used /modified / copied only in accordance with the terms of such license.
Environmental Protection
To confront directly with the responsibility toward the environment, the global community and eventually also oneself. Such a resolution should be integral part not only of everybody's life. Also enterprises shall be conscious of their social responsibility and contribute to the preservation of our common living space. That is why Trenz Electronic invests in the protection of our Environment.
REACH, RoHS and WEEE
REACH
Trenz Electronic is a manufacturer and a distributor of electronic products. It is therefore a so called downstream user in the sense of REACH. The products we supply to you are solely non-chemical products (goods). Moreover and under normal and reasonably foreseeable circumstances of application, the goods supplied to you shall not release any substance. For that, Trenz Electronic is obliged to neither register nor to provide safety data sheet. According to present knowledge and to best of our knowledge, no SVHC (Substances of Very High Concern) on the Candidate List are contained in our products. Furthermore, we will immediately and unsolicited inform our customers in compliance with REACH - Article 33 if any substance present in our goods (above a concentration of 0,1 % weight by weight) will be classified as SVHC by the European Chemicals Agency (ECHA).
RoHS
Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.
WEEE
Information for users within the European Union in accordance with Directive 2002/96/EC of the European Parliament and of the Council of 27 January 2003 on waste electrical and electronic equipment (WEEE).
Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.
Trenz Electronic is registered under WEEE-Reg.-Nr. DE97922676.
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