Table of contents
Overview
Firmware for PCB-Slave CPLD with designator U39. Second CPLD Device in Chain: LCMX02-1200HC
Feature Summary
Firmware Revision and supported PCB Revision
See Document Change History
Product Specification
Port Description
Name | Direction | Pin | Description |
---|---|---|---|
1.8V_EN / EN_1V8 | out | 106 | Power |
5V_EN | 115 | (currently controlled via S4-4) / currently_not_used | |
C_TCK | 131 | JTAG J28 (XMOD2) / internal currently_not_used | |
C_TDO | 137 | JTAG J28 (XMOD2) / internal currently_not_used | |
C_TDO1 | 136 | JTAG J28 (XMOD2) / internal currently_not_used | |
C_TMS | 130 | JTAG J28 (XMOD2) / internal currently_not_used | |
CLK_A / AUD_CLK | out | 1 | AUDIO U3 CLK |
CLK_CPLD / MEMS_CLKIN | in | 128 | U25 24,576MHz |
DONE | in | 67 | PS Done / currently_not_used |
EN_DDR | out | 86 | Enable DDR Power |
EN_FMC / FMC_EN | out | 104 | FMC |
EN_FPD | out | 81 | Enable PS FPD Power |
EN_GT_L | out | 77 | Enable GT Power |
EN_GT_R | out | 93 | Enable GT Power |
EN_LPD | out | 84 | Enable PS LPL Power |
EN_PL | out | 95 | Enable PL Power |
EN_PLL_PWR | out | 78 | Enable SI5345 Power |
EN_PSGT / EN_PSGTR | out | 75 | Enable PS GT Power |
ERR_OUT / ERROR | in | 70 | PS Error Out / currently_not_used |
ERR_STATUS / ERROR_STAT | in | 69 | PS Error Status / currently_not_used |
F1PWM | out | 121 | FAN1 |
F1SENSE | in | 125 | FAN1 |
FAN_FMC_EN | out | 132 | FMC FAN |
FMC_PG_C2M | 141 | FMC / currently_not_used | |
HD_LED_N / HDLED_N | out | 112 | J10 HD LED |
HD_LED_P / HDLED_P | out | 110 | J10 HD LED |
HDIO_SC0 / SC0 | in | 32 | FPGA IO |
HDIO_SC1 / SC1 | in | 33 | FPGA IO |
HDIO_SC2 / SC2 | in | 34 | FPGA IO |
HDIO_SC3 / SC3 | out | 35 | FPGA IO |
HDIO_SC4 / SC4 | out | 25 | FPGA IO |
HDIO_SC5 / SC5 | out | 26 | FPGA IO |
HDIO_SC6 / SC6 | in | 27 | FPGA IO / CLK |
HDIO_SC7 / SC7 | in | 28 | FPGA IO |
I2C_SCL / SCL | in | 50 | I2C / currently_not_used |
I2C_SDA / SCA | in | 52 | I2C / currently_not_used |
INIT_B / INIT | in | 68 | PS init B / currently_not_used |
JTAGENB | | 120 | external Pin for CPLD Firmware Update |
LP_GOOD / PG_LPD | in | 83 | LP Power Good / currently_not_used |
MIO24 | 38 | MIO / currently_not_used | |
MIO25 | 39 | MIO / currently_not_used | |
MIO30 | 48 | MIO / currently_not_used | |
MIO31 | in | 49 | MIO / currently_not_used |
MIO32 | 40 | MIO / currently_not_used | |
MIO33 | 41 | MIO / currently_not_used | |
MIO34 | 42 | MIO / currently_not_used | |
MIO35 | 43 | MIO / currently_not_used | |
MIO36 | 44 | MIO / currently_not_used | |
MIO37 | 45 | MIO / currently_not_used | |
MIO40 | 54 | MIO / currently_not_used | |
MIO41 | 55 | MIO / currently_not_used | |
MIO42 | out | 60 | FPGA UART RX |
MIO43 | in | 61 | FPGA UART TX |
MIO44 | 47 | / currently_not_used | |
MOD_EN | out | 119 | Module Power 3.3V Enable |
MODE0 | out | 6 | Boot Mode |
MODE1 | out | 9 | Boot Mode |
MODE2 | out | 10 | Boot Mode |
MODE3 | out | 11 | Boot Mode |
MR / MRESETn | out | 92 | PS Reset |
PCI_SFP_EN | out | 76 | SFP |
PER_EN | out | 117 | Baseboard Power 3.3V Enable |
PERST / PERSTn | out | 139 | PCIE Resetn |
PG_DDR | in | 91 | Power Good / currently_not_used |
PG_FPD | in | 85 | Power Good / currently_not_used |
PG_GT_L | in | 96 | Power Good / currently_not_used |
PG_GT_R | in | 94 | Power Good / currently_not_used |
PG_PL | in | 82 | Power Good / currently_not_used |
PG_PLL_1V8 / PG_PLL | in | 73 | Power Good / currently_not_used |
PG_PSGT | in | 74 | Power Good / currently_not_used |
PLL_LOLN / PLL_LOL | in | 58 | Module U5 Si5345 / currently_not_used |
PLL_RST / PLL_RSTn | out | 56 | Module U5 Si5345 |
PLL_SEL0 | out | 57 | Module U5 Si5345 |
PLL_SEL1 | out | 59 | Module U5 Si5345 |
POK_1V8 | 107 | Power / currently_not_used | |
POK_FMC | 99 | FMC Power/ currently_not_used | |
PROG_B | inout | 71 | PS_PROG_B |
PSON | out | 105 | ATX J20 PS_ON_N |
PWR_BTN | in | 113 | Power Button S1 or J10 |
PWRLED_N / LED_N | out | 111 | J10 PWR |
PWRLED_P / LED_P | out | 109 | J10 PWR |
PWROK | in | 100 | ATX J20 PWROK |
RST_BTN | in | 114 | Reset Button S2 or J10 |
S_1 | 127 | Beeper/ currently_not_used | |
SC_IO0 / X0 | out | 12 | Master-Slave SC-Communication / Power Reset |
SC_IO1 / X1 | out | 13 | Master-Slave SC-Communication / Power Reset |
SC_IO2 / X2 | out | 14 | Master-Slave SC-Communication / currently_not_used |
SC_IO3 / X3 | out | 20 | Master-Slave SC-Communication / currently_not_used |
SC_IO4 / X4 | in | 21 | Master-Slave SC-Communication / currently_not_used |
SC_IO5 / X5 | in | 22 | Master-Slave SC-Communication / currently_not_used |
SC_IO6 / X6 | in | 23 | Master-Slave SC-Communication / Sanity check from other CPLD (FMC VADJ Enable) |
SC_IO7 / X7 | in | 24 | Master-Slave SC-Communication / Sanity check from other CPLD (FMC VADJ Enable) |
SC_IO8 / dummy | 126 | / currently_not_used / ! not available on PCB REV2 ! | |
SC2_SW1 | in | 133 | S5-1 / Boot Mode Selection |
SC2_SW2 | in | 138 | S5-2 / Boot Mode Selection |
SD_A_EN | out | 140 | Micro SD |
SD_B_EN | out | 122 | MMC SD |
SD_CD / SD_CD_OUT | out | 65 | SD Card detect to FPGA |
SD_CD_B | in | 143 | MMC SD |
SD_CD_S | in | 142 | Micro SD |
SEL_SD / SD_SEL | out | 62 | Select SD |
SRST_B / SRSTn | out | 19 | PS_SRST_B |
STAT_LED2 / LED2 | out | 98 | LED D6 Green |
STAT_LED3 / LED3 | out | 97 | LED D7 Red |
XMOD2_A / XMOD_TXD | out | 5 | J12 (XMOD 1) |
XMOD2_B / XMOD_RXD | in | 4 | J12 (XMOD 1) |
XMOD2_E / XMOD_LED | out | 3 | J12 (XMOD 1) |
XMOD2_G / XMOD_BTN | in | 2 | J12 (XMOD 1) |
Functional Description
JTAG
JTAGENB set carrier board CPLD into the chain for firmware update. For Update set DIP S4-3 to ON.
Power
PSON signal will be enabled/disabled after delay, when Power Button is pressed.
ATX PSON is set by PSON signal. This enable/disable 12V power supply from ATX connector.
PCI and SFP Power is always enabled, if 12V is available.
Module 3.3V is always enabled, if 12V is available.
Baseboard 3.3V is always enabled, if 12V is available.
Module PS LPL Power is always enabled, if 12V is available.
Module PS FPD Power is always enabled, if 12V is available.
Module PL Power is always enabled, if 12V is available.
Module DDR Power is always enabled, if 12V is available.
Module PLL Power is always enabled, if 12V is available.
Module PS GT Power is always enabled, if 12V is available.
Module PL GT L/R Power is always enabled, if 12V is available.
TE0808 module is not completely powered off with power button, if 12V power jack (J25) is used for power supply. 12V Power ON/OFF is currently only for ATX connector implemented.
Enable
SD's will be enabled by PSON.
FMC_FAN_EN will be enabled by PSON or RGPIO (11) controlled, when active.
Reset
Name | Description |
---|---|
PLL_RSTn | not RGPIO (0) when active else '1' |
SRSTn | not RGPIO (1) when active else '1' |
MRESETn | not RGPIO (2) when active else RST_BTN |
PERSTn | not RGPIO (3) when active else PWR_BTN |
Master CPLD Reset | with PSON and Reset Button over CPLD interconnect. |
Boot Mode
S4-1 | S4-2 | Description |
---|---|---|
ON | ON | Default, boot from SD/eMMC or SPI Flash if no SD is detected |
OFF | ON | Boot mode PJTAG0 |
ON | OFF | Boot from eMMC |
OFF | OFF | Boot mode main JTAG |
If MicroSD is detected, the system boots from this SD-Card independents from S4 setting.
UART
XMOD_TXD is sourced by MIO43 and MIO42 by XMOD_RXD.
Module SI5345
Module U5 Selection Pins are set fix to zero.
RGPIO
RGPIO Pin to FPGA | Value |
---|---|
0 | SW1 |
1 | SW2 |
2 | RST_BTN |
3 | PWR_BTN |
4 | SD_CD_S |
5 | SD_CD_B |
6 | F1SENSE |
7 | PWROK |
8 | XMOD_BTN |
9-19 | unused |
20 | PLL_LOL |
21-23 | unused |
24-27 | reserved |
28-31 | Interface detection |
RGPIO Pin from FPGA | Value |
---|---|
0 | PLL_RSTn |
1 | SRSTn |
2 | MRESETn |
3 | PERSTn |
4 | PROG_B |
5 | LED2 |
6 | LED3 |
7 | LED_N |
8 | LED_P |
9 | HDLED_N |
10 | HDLED_P |
11 | FMC_FAN_EN |
12-23 | unused |
24-27 | reserved |
28-31 | Interface detection |
LED
Name | Description |
---|---|
LED2 D6 Green | RGPIO (5) when active else slow_blink when PSON is off else on |
LED3 D7 Red | RGPIO (6) when active else not RST_BTN or mode_blink |
LED_N | RGPIO (7) when active else off |
LED_P | not RGPIO (8) when active else slow_blink when PSON is off else on |
HDLED_N | RGPIO (9) when active else off |
HDLED_P | not RGPIO (10) when active else reset Button is pressed |
XMOD_LED Red | Done Pin: ON is not programmed, OFF programmed |
*slow_blink: ~0,7 Hz
*mode_blink:
Mode Blink Sequence Comment Error ******** ~5,8 Hz JTAG *****ooo ~0,7 Hz, duty cycle 5/8 PJTAG0 ****oooo ~0,7 Hz, duty cycle 4/8 eMMC ***ooooo ~0,7 Hz, duty cycle 3/8 SPI Boot **oooooo ~0,7 Hz, duty cycle 2/8 SD Boot *ooooooo ~0,7 Hz, duty cycle 1/8
Appx. A: Change History and Legal Notices
Revision Changes
Older Revision (PCB REV03) to CPLD REV04
- Bugfix: PCIe Reset Pin location.
- Bugfix: Swapping HDLED and PWRLED location.
- Bugfix: MEMS_CLKIN Pin location.
- Add XMOD 1 LED
Older Revision (PCB REV02) to CPLD REV04
- Add all functionality from older Revision (PCB REV03)
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description |
---|---|---|---|---|---|
| REV04 | REV02, REV03, REV04 | Revision 04 finished | ||
2016-04-11 | v.1 | --- | Initial release | ||
All |
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