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Table of Contents
Overview
The Cyclone10 LP Reference Kit is the world's first development board with a 55kLE Intel Cyclone 10 LP and a variety of interfaces for numerous applications. The board is comprehensively tested and ready for use with end products and can also be ordered in customer-specific variants according to your requirements.
Refer to http://trenz.org/tei0009-info for the current online version of this manual and other available documentation.
Key Features
- Intel® Cyclone 10 LP [10CL055YU484C8G],
- Package: UBGA-484
- Speed Grade: 8 (Slowest)
- Temperature: 0°C ~ 85°C
- Package compatible device 10CL016, 10CL040, 10CL080 as assembly variant on request is possible
- 16 MBit flash memory (optional up to 32 MBit possible)
- Integrated USB2.0 Programmer
- Pin Header connectors
- 256 MBit (optional up to 512 MBit possible) SDRAM
- 128 MBit (optional up to 512 MBit possible) User Quad-SPI Flash memory
- 64 MBit HyperRAM(Pseudo SRAM) (optional up to 128 MBit possible)
- FTDI - System Controller (CPLD)
- 2x MAC address EEPROM
- 2x Fast Ethernet PHY (10/100 Mbps)
- 8-channel, 12-bit, configurable ADC /DAC with on-chip reference
- D-Sub connector
- 2x RJ45 connector
- LEDs:
- Status LEDs, Power LED
- 13x User LEDs
- 7-segment display
- Push bottuns:
- 2x Reset Push buttons
- 5x User Push buttons
- I/O:
- GPIO: 321
- LVDS: 132
- Power Supply:
- 5 V
- Minimum 1A
- Others:
- Reverse polarity of supply voltage protection
- Under/Over voltage protection
Block Diagram
Main Components
- Barrel Jack, J12
- RJ45 socket, J8...9
- D-Sub Connector, J11
- Push button(Reset), S7
- Grove connector, J5
- Under/Over Voltage Protecter, U9
- 7-segment LED, D11
- 1x6 pin header, J4
- 1x8 pin header, J2...3
- User Red LEDs, D2...9
- 8x User Red LEDs, D13...17
- 5x User Push buttons, S1- S3...6
- Red LED (CONF_DONE), D10
- PSRAM memory, U3
- SDRAM memory, U10
- Voltage Regulator, U5- U7
- AD/DA Convertor, U2
- Pmod 2x6 SMD host socket, P1...6
- Intel®Cyclone 10 LP, U1
- Configuration memory, U5
- 1x10 pin header, J1
- EEEPROM, U15- U18- U20
- FTDI USB2 to JTAG/UART adapter, U14
- Micro USB 2.0 (receptacle) J10
- Push button (RST_GPIO), S2
- Oscillator, U22
- Ethernet PHY, U17- U19
- QSPI Flash memory, U12
Initial Delivery State
Storage device name | Content | Notes |
---|---|---|
QSPI Flash | Not programmed | |
EEPROM | Programmed | FTDI configuration |
SDRAM | Not programmed | |
PSRAM | Not programmed | |
FTDI System Controller CPLD | Not programmed | |
Configuration Memory | Demo Design |
Configuration Signals
Configuration mode has been set to AS (Active Serial) configuration.
MODE Signal State | MSEL0 | MSEL1 | MSEL2 | MSEL3 | Connected to | Boot Mode |
---|---|---|---|---|---|---|
MSEL[0:3] | 0 | 1 | 0 | 0 | Bank 6 | AS (Active Serial) |
RESET pin can be set through the push button S1.
Signal | Connected to | Note |
---|---|---|
RESET | S7 (Push button) | Connected to nCONFIG |
RST_GPIO | S2 (Push button) | |
EXT_RST | J3 (1x8 pin header) Bank 2 |
Signals, Interfaces and Pins
I/Os on Pin Headers and Connectors
FPGA bank number and number of I/O signals connected to the B2B connector:
FPGA Bank | Connector | I/O Signal Count | Voltage Level | Notes |
---|---|---|---|---|
Bank 1 | J1 (Pin header) | 8 Single ended | 3.3 V | |
J2 (Pin header) | 8 Single ended | 3.3 V | ||
J4 (Pin header) | 6 Single ended | 3.3 V | ||
Bank 2 | J3 (Pin header) | 1 Single ended | 3.3 V | |
P1 (PMod SMD host socket) | 8 Single ended | 3.3 V | ||
P2 (PMod SMD host socket) | 8 Single ended | 3.3 V | ||
J11 (VGA host Socket) | 14 Single ended | 3.3 V | ||
Bank 6 | J5 (Grove connector) | 2 Single ended | 3.3 V | |
Bank 7 | P5 (PMod SMD host socket) | 8 Single ended | 3.3 V | |
P6 (PMod SMD host socket) | 8 Single ended | 3.3 V | ||
Bank 8 | P3 (PMod SMD host socket) | 8 Single ended | 3.3 V | |
P4 (PMod SMD host socket) | 8 Single ended | 3.3 V |
PMod SMD Host Socket
TEI0009 has 6 PMod 2x6 SMD Host Socket 90° which are connected to Cyclon 10 LP (U1).
Designator | Signals | Connected to | Notes |
---|---|---|---|
P1 | P1_IO1...8 | Bank 2 | |
P2 | P2_IO1...8 | Bank 2 | |
P3 | P3_IO1...8 | Bank 8 | |
P4 | P4_IO1...8 | Bank 8 | |
P5 | P5_IO1...8 | Bank 7 | |
P6 | P6_IO1...8 | Bank 7 |
UART Interface
UART access to TEI0009 is available on 1x8 pin header J2.
Schematic | Pin Header | Connected to | Voltage Level | Notes |
---|---|---|---|---|
TXD | J2 | Bank 1 | 3.3 V | |
RXD | J2 | Bank 1 | 3.3 V |
Micro USB2.0 Connector
U14(FTDI FT2232) can be accessed through Micro USB2.0 B Receptacle 90 (J10).
Schematic | Connected to | Voltage Level | Notes |
---|---|---|---|
USB_VBUS | GND | ||
D- | U14 (FTDI FT2232) | 3.3 V | |
D+ | U14 (FTDI FT2232) | 3.3 V |
RJ45 Connectors
TEI0009 is equipped with two RJ45 connectors and two Ethernet PHYs. RJ45 connectors J8 and J9 are connected to Ethernet PHYs U17 and U19 respectively. .
Pin | Schematic | ETH1 Pin | ETH2 Pin | Notes |
---|---|---|---|---|
TD+ | ETH_TX_P | U17- TXP | U19- TXP | |
CT | ETH_CTREF_TCT | - | - | Connected to GND |
TD- | ETH_TX_N | U17- TXM | U19- TXM | |
RD+ | ETH_RX_P | U17- RXP | U19- RXP | |
CT | ETH_CTREF_RCT | - | - | Connected to GND |
RD- | ETH_RX_N | U17- RXM | U19- RXM | |
LED Green | ETH_LED0 | U17- NWAYEN | U19- NWAYEN | |
LED Yellow | ETH_LED1 | U17- SPEED | U19- SPEED |
D-Sub Connectors
TEI0009 is equipped with a D-Sub connector (Receptacle) which provides interface to Cyclone 10 LP through Bank 2.
Schematic | Corresponding Signals | Connected to | Notes |
---|---|---|---|
VGA_RED | VGA_R0...3 | Bank 2 | Red channel |
VGA_GREEN | VGA_G0...3 | Bank 2 | Green channel |
VGA_BLUE | VGA_B0...3 | Bank 2 | Blue channel |
VGA_RGB_HSYNC | VGA_HS | Bank 2 | Horizontal sync |
VGA_RGB_VSYNC | VGA_VS | Bank 2 | Vertical sync |
On-board Peripherals
Chip/Interface | Designator | Notes |
---|---|---|
QSPI Flash memory | U12 | |
SDRAM memory | U10 | |
PSRAM memory | U3 | |
7 Segment LED | D11 | |
FTDI FT2232 | U14 | |
Ethernet PHY | U17, U19 | |
Configuration Memory | U5 | |
ADC/DAC | U2 | |
EEPROM | U15, U18, U20 | |
User LEDs | D2...D17 | |
Oscillators | U16, U22 |
QSPI Flash Memory
There is a 64MBit QSPI Flash memory (U12) provided by Winbond which can be used to store data or configuration.
Pin | Schematic | Connected to | Notes |
---|---|---|---|
CS | F_CS | Bank 7 | |
CLK | F_CLK | Bank 7 | |
IO0...3 | F_IO0...3 | Bank 7 |
SDRAM Memory
The TEI0009 has 256 MBit volatile provided by Winbond , SDRAM IC(U10) for storing user application code and data. Up to 512 MBit SDRAM is possibleon other assembly option.
Part number: W9864G6JT-6-ND
Supply voltage: 3.3 V
- Clock Frequency: 166MHz
Temperature: 0°C ~ 70°C
PSRAM Memory
The TEI0009 is integrated with 64Mbit Pseudo Static Random Access Memory (PSRAM) using a self-refresh DRAM array organized as 8M words by 8 bits. The device supports a HyperBus interface, Very Low Signal Count (Address, Command and data through 8 DQ pins), Hidden Refresh Operation, and Automotive Temperature Operation.
Part number: IS66WVH8M8BLL
Supply voltage: 3.3 V
- Clock Frequency: 100MHz
Temperature: -40°C ~ 85°C
7 Segment LED
The TEI0009 has a LED 7 Segment- 4 Digit which is connected to Bank 6.
Pin | Schematic | Connected to | Notes |
---|---|---|---|
A/L1 | SEG_CA | Bank 6 | |
B/L2 | SEG_CB | Bank 6 | |
C/L3 | SEG_CC | Bank 6 | |
D | SEG_CD | Bank 6 | |
E | SEG_CE | Bank 6 | |
F | SEG_CF | Bank 6 | |
G | SEG_CG | Bank 6 | |
DP | SEG_CDP | Bank 6 | |
A1 | SEG_AN | Bank 6 | |
A2 | SEG_AN4 | Bank 6 | |
A3 | SEG_AN3 | Bank 6 | |
A4 | SEG_AN2 | Bank 6 | |
L1-L3 | SEG_AN1 | Bank 6 |
FTDI FT2232
The FTDI chip U14 converts signals from USB2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H chip.
FTDI FT2232H chip is used in MPPSE mode for JTAG, 6 I/O's of Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.
The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U15.
FTDI Chip Pin | Signal Schematic Name | Connected to | Notes |
---|---|---|---|
ADBUS0 | TCK | Bank 1 | JTAG interface |
ADBUS1 | TDI | Bank 1 | |
ADBUS2 | TDO | Bank 1 | |
ADBUS3 | TMS | Bank 1 | |
BDBUS0 | BDBUS0 | Bank 6 | |
BDBUS1 | BDBUS1 | Bank 6 | |
BDBUS2 | BDBUS2 | Bank 6 | |
BDBUS3 | BDBUS3 | Bank 6 | |
BDBUS4 | BDBUS4 | Bank 6 | |
BDBUS5 | BDBUS5 | Bank 6 | |
EECS | EECS | U15 (EEPROM) | |
EECLK | EECLK | U15 (EEPROM) | |
EEDATA | EEDATA | U15 (EEPROM) | |
OSCI | CK12M | U16 (12MHz Oscillator) | |
DM | D_N | J10 (Micro USB2.0) | |
DP | D_P | J10 (Micro USB2.0) |
Configuration Memory
On-board serial configuration memory (U5) is provided by Intel with 16 MBit (2 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 1 via active serial (AS) x1 interface.
Configuration Memory Pin | Signal Schematic Name | Connected to | Notes |
---|---|---|---|
DATA1 | AS_DATA0 | U1, Bank 1 | Data out |
DATA0 | AS_ASDO | U1, Bank 1 | Data in |
nCS | AS_NCS | U1, Bank 1 | chip select |
DCLK | AS_DCLK | U1, Bank 1 | clock |
Ethernet PHY
The TEI0009 is equipped with two Ethernet PHY (U19, U17) which are connected to two RJ45 connectors.
Ethernet PHY Pin | Signal Schematic Names | ETH 1 | ETH 2 | Note |
---|---|---|---|---|
TXD0...3 | ETH_TXD0...3 | Bank 5 | Bank 5 | |
TXC | ETH_TXC | Bank 5 | Bank 5 | |
TXEN | ETH_TXEN | Bank 5 | Bank 5 | |
RXD0...3 | ETH_RXD0...3 | Bank 5 | Bank 5 | |
RXC//B-CAST_OFF | ETH_RXC | Bank 5 | Bank 5 | |
RXER/ISO | ETH_RXER | Bank 5 | Bank 5 | |
INTRP//NAND_Tree | ETH_INTRP | Bank 5 | Bank 5 | |
XI | ETH_CLKIN | U22 (Oscillator) | U22 (Oscillator) | |
MDC | ETH_MDC | Bank 5 | Bank 5 | |
MDIO | ETH_MDIO | Bank 5 | Bank 5 | |
COL/CONFIG0 | ETH_COL | Bank 5 | Bank 5 | |
CRS/CONFIG1 | ETH_CRS | Bank 5 | Bank 5 | |
RXDV/CONFIG2 | ETH_RXDV | Bank 5 | Bank 5 | |
LED0/NWAYEN | ETH_LED0 | Bank 5 J8B (RJ45- Green LED) | Bank 5 J9B (RJ45-Green LED) | |
LED1/SPEED | ETH_LED1 | Bank 5 J8C (RJ45-Yellow LED) | Bank 5 J9B (RJ45-Yellow LED) | |
nRST | ETH_RST | Bank 5 | Bank 5 | |
RXM | ETH_RX_N | J8 (RJ45) | J9 (RJ45) | |
RXP | ETH_RX_P | J8 (RJ45) | J9 (RJ45) | |
TXM | ETH_TX_N | J8 (RJ45) | J9 (RJ45) | |
TXP | ETH_TX_P | J8 (RJ45) | J9 (RJ45) |
EEPROM
TEI0009 has three EEPROM, U15, U18 and U20. U15 is pre-programmed by FTDI FT2232H configuration.
Designator | EEPROM Pin | Signal Schematic Names | Connected to | Notes |
---|---|---|---|---|
U15 | CS | EECS | U14 (FTDI) | |
CLK | |EECLK | U14 (FTDI) | ||
DIN/DOUT | EEDATA | U14 (FTDI) | FTDI Configuration |
Designator | Pin | Schematic | Connected to | Grove Header | Notes |
---|---|---|---|---|---|
U18, U20 | SCL | I2C_SCL | Bank 6 | J5 | |
SDA | I2C_SDA | Bank 6 | J5 |
I2C Address | Designator | Notes |
---|---|---|
0x50 | U18 | |
0x52 | U20 |
ADC/DAC
The TEI0009 module is equipped with 12bit ADC/DAC (U2).
Pins | Schematic | Connected to | Notes |
---|---|---|---|
nRESET | ADDA_RSTN | U1, Bank 2 | VREF_ADC |
nSYNC | ADDA_SYNC | U1, Bank 2 | |
SCLK | MCLK | U1, Bank 2 | |
SDI | MSDI | U1, Bank 2 | |
SDO | MSDO | U1, Bank 2 | |
VREF | - | U1, Bank 2 | External reference is 1 V to 3.3V Internal reference is 2.5 V |
IO0...5 | AIN0...5 | U1, Bank 1 J4, Pin header |
LEDs
Schematic | Designator | Color | Connected to | Active Level | Note |
---|---|---|---|---|---|
LED1...8 | D2...9 | Red | Bank 3 | High | |
LED_PB1 | D13...17 | Red | Bank 7 | High | |
CONF_DONE | D10 | Red | Bank 6 | Low |
Clock Sources
Designator | Description | Frequency | Note |
---|---|---|---|
U22 | MEMS Oscillator | 25 MHz | |
U16 | MEMS Oscillator | 12 MHz |
Power and Power-On Sequence
Power Supply
Power supply with minimum current capability of 1A for system startup is recommended.
Power Consumption
FPGA | Typical Current |
---|---|
Intel Cyclone 10 LP FPGA | TBD* |
* TBD - To Be Determined
Power Distribution Dependencies
Power-On Sequence
There is no power on sequence, After power on, all regulators will be enabled as you can see in the diagram below.
Voltage Monitor Circuit
There is a diod (D12) which protects the board from reverse polarity, Additionaly there is an Over/under voltage (IC) which protects the board from over voltage damages.
Power Rails
Connector Designator | VCC / VCCIO Schematic Name | Pin | Direction | Notes |
---|---|---|---|---|
J3 | 3.3V | 2,4 | Out | |
5V | 5 | Out | ||
J5 | 3.3V | 3 | Out |
Bank Voltages
Bank | Schematic Name | Voltage | Notes |
---|---|---|---|
Bank 1 | VCCIO1 | 3.3V | |
Bank 2 | VCCIO2 | 3.3V | |
Bank 3 | VCCIO3 | 3.3V | |
Bank 4 | VCCIO4 | 3.3V | |
Bank 5 | VCCIO5 | 3.3V | |
Bank 6 | VCCIO6 | 3.3V | |
Bank 7 | VCCIO7 | 3.3V | |
Bank 8 | VCCIO8 | 3.3V |
Technical Specifications
Absolute Maximum Ratings
Symbols | Description | Min | Max | Unit | Note |
---|---|---|---|---|---|
VIN | Input supply voltage | -5.0 | 5.0 | V | |
VCCIO | I/O buffers power supply | -0.5 | 3.75 | V | |
VCCINT | Core voltage | -0.5 | 1.8 | V | |
VCCD_PLL | PLL digital power supply | -0.5 | 1.8 | V | |
VCCA | Phase-locked loop (PLL) analog power supply | -0.5 | 3.75 | V | |
V_AN | Analog Input Voltage on ADC/DAC (U2) | -0.3 | 3.6 | V | |
V_DIG | Digital Input Voltage on ADC/DAC (U2) | -0.3 | 3.6 | V | |
V_REF_IN | Internal Reference Voltage Voltage on ADC/DAC (U2) | -0.3 | 3.6 | V | |
V_REF_EX | External Reference Voltage Voltage on ADC/DAC (U2) | -0.3 | 3.6 | V | |
T_STG | Storage Temperature | -35 | 85 | °C | See LTC2623WC datasheet |
Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Parameter | Min | Max | Units | Reference Document |
---|---|---|---|---|
VIN | 4.75 | 5.25 | V | |
VCCIO | 3.135 | 3.465 | V | See Cyclone 10 LP datasheet. |
VCCINT | 1.15 | 1.25 | V | See Cyclone 10 LP datasheet. |
VCCD_PLL | 1.15 | 1.25 | V | See Cyclone 10 LP datasheet. |
VCCA | 2.375 | 2.625 | V | See Cyclone 10 LP datasheet. |
V_AN | 0 | 3.3 | V | See AD5592RBCPZ datasheet. |
V_DIG | 0 | 3.3 | V | See AD5592RBCPZ datasheet. |
V_REF_IN | 1 | 3 | V | See AD5592RBCPZ datasheet. |
V_REF_EX | 2.45 | 2.55 | V | See AD5592RBCPZ datasheet. |
T_OP | 0 | 70 | °C | See SDRAM W9864G6JT datasheet |
Physical Dimensions
Module size: 95 mm × 110 mm. Please download the assembly diagram for exact numbers.
- PCB thickness: 1.6 mm.
Currently Offered Variants
Trenz shop TE0728 overview page | |
---|---|
English page | German page |
Revision History
Hardware Revision History
Date | Revision | Changes | Document Link |
---|---|---|---|
2018-2-19 | 01 | - | REV01 |
2018-7-18 | 02 |
| REV02 |
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Document Change History
Date | Revision | Contributor | Description |
---|---|---|---|
| |||
-- | all |
|
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