|Company||Trenz Electronic GmbH|
|Title||TE0820-03 to TE0820-04 Hardware Revision Change|
|Subject||Hardware Revision Change|
This change affects all Trenz Electronic TE0820 SoMs of revision 03: TE0820-03-*.
1. Added a VRP resistor on bank 65;
2. LDO U33 is changed on ADP7102ACPZ;
3. Signal FPGA IO0 is connected on AE18 pin of FPGA;
4. Signal DBG_LED3 is connected on AD18 pin of FPGA;
5. Signal MIO13_25 connected to J1 pin 33 instead MIO25.
6. Resistor R84 is removed;
7. LED D1 moved on edge of PCB;
8. Added THT testpoints J4 on CPLD_JTAGEN, R76 was removed;
9. Signals B49_XX_X are renamed in B88_XX_X;
10. C241 is changed on 1nF;
11. Length of CLK signals on RFADC and RFDAC are adjusted;
12. Wrong connection on U8 is fixed (PCB);
13. Wrong connection PGOOD1 pin of U7 is fixed;
Method of Identification
The revision number is printed in the top side of the PCB.
Production Shipment Schedule
If you have any questions related to this PCN, please contact Trenz Electronics Technical Support at
- support%trenz-electronic.de (subject = PCN-20200616)
national calls: 05741 3200-0
international calls: 0049 5741 3200-0
Any projected dates in this PCN are based on the most current product information at the time this PCN is being issued, but they may change due to unforeseen circumstances. For the latest schedule and any other information, please contact your local Trenz Electronic sales office, technical support or local distributor.
This PCN follows JEDEC Standard J-STD-046.